Semiconductor device with buried local interconnects

1. A method for fabricating a semiconductor device with buried local interconnects, the method comprising:

providing a semiconductor substrate comprising a plurality of fins etched in the semiconductor substrate;

forming a first set of spacers along sides of the plurality of fins, wherein the one or more insulating materials and the first set of spacers are recessed to a same level;

depositing a tungsten film over a top surface of the semiconductor substrate;

etching the tungsten film to form one or more buried local interconnects;

forming a set of gates and a second set of spacers adjacent to the set of gates, wherein a portion of the gate structure and the second set of spacers are disposed around the plurality of fins;

patterning a buried local interconnect wire, wherein the buried local interconnect wire comprises a buried local interconnect and an upper buried local interconnect, wherein tungsten is patterned throughout the semiconductor substrate such that a portion of tungsten that remains after the patterning forms the buried local interconnects and the upper buried local interconnect;

forming a source and drain region, adjacent to the plurality of fins;

depositing a first insulating material over the top surface of the semiconductor substrate; and

creating contact between the set of gates and the source and drain region using an upper buried local interconnect.

2. The method of claim 1 , further comprising:

removing a top layer of the tungsten film using a planarization process, wherein the planarization process comprises one of: chemical mechanical polishing (CMP), grinding, organic dielectric layer (ODL) spin, and a combination of CMP and reactive ion etching (RIE).

3. The method of claim 1 , wherein the plurality of fins are etched in the semiconductor substrate using reaction ion etching (RIE).

4. The method of claim 1 , further comprising:

creating device regions in the semiconductor substrate using shallow trench isolation (STI);

filling the device regions with a second insulating material; and

planarizing the second insulating material.

5. The method of claim 1 , further comprising:

depositing a hard mask over the semiconductor substrate; and

etching one or more recesses into the semiconductor substrate to form a set of fins.

6. The method of claim 1 , wherein depositing a first insulating material over the top surface of the semiconductor substrate comprises one of: chemical vapor deposition (CVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD).

7. The method of claim 1 , wherein depositing a first insulating material over the top surface of the semiconductor substrate further comprises planarization of the first insulating material, wherein the planarization exposes an upper surface of the set of gates.

8. The method of claim 1 further comprising:

creating a plurality shallow trench isolations, wherein the plurality of shallow trench isolations are filled to a depth between 20 nm-30 nm with one or more insulation materials.

9. The method of claim 1 further comprising:

Etching the tungsten film to form one or more buried local interconnects.