Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
View Patent ↗A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions.
1. A semiconductor structure comprising:
a semiconductor substrate;
an epitaxial blanket layer comprising III-V semiconductor material on a top surface of the semiconductor substrate, the epitaxial blanket layer comprising a first III-V semiconductor sub-layer directly contacting the semiconductor substrate and a second III-V semiconductor sub-layer over the first III-V semiconductor layer, the second III-V semiconductor sub-layer having a larger lattice constant than the first III-V semiconductor sub-layer, the first III-V semiconductor sub-layer including misfit defects;
a plurality of parallel, dielectric regions extending vertically from and adjoining a top surface of the epitaxial blanket layer, the parallel, dielectric regions defining a plurality of vertically extending trenches, and
an epitaxial second layer comprising III-V semiconductor material directly contacting the second III-V semiconductor sub-layer of the epitaxial blanket layer and positioned within the vertically extending trenches.
2. The semiconductor structure of claim 1 , wherein the first III-V semiconductor sub-layer directly contacts the second III-V semiconductor sub-layer.
3. The semiconductor structure of claim 2 , wherein the first III-V semiconductor sub-layer comprises gallium arsenide.
4. The semiconductor structure of claim 1 , wherein the semiconductor substrate comprises at least one of silicon and germanium.
5. The semiconductor structure of claim 4 , wherein at least a portion of the epitaxial blanket layer and the epitaxial second layer are comprised of the same III-V semiconductor material.
6. The semiconductor structure of claim 4 , wherein the dielectric regions and the epitaxial second layer have the same depth.
7. The semiconductor structure of claim 4 , wherein the vertically extending trenches each have a depth dimension and a width dimension, the depth dimension being at least three times the width dimension.
8. The semiconductor structure of claim 7 , wherein the dielectric regions and the epitaxial second layer have coplanar top surfaces.
9. The semiconductor structure of claim 7 , wherein the second III-V semiconductor sub-layer comprises indium gallium arsenide and the first III-V semiconductor sub-layer comprises gallium arsenide.
10. The semiconductor structure of claim 7 , wherein the semiconductor substrate consists essentially of silicon.
11. The semiconductor structure of claim 7 , wherein the epitaxial second layer has the same lattice constant as the second III-V semiconductor sub-layer of the epitaxial blanket layer.