Formation of strained fins in a finFET device
View Patent ↗In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (SiGe) and an upper portion that is comprised of semiconductor material. In one aspect, a first set of one or more fins that include an upper portion comprised of a first semiconductor material. In another aspect, a second set of one or more fins that include an upper portion comprised of a second semiconductor material.
1. A field-effect transistor (FET) structure comprising:
a plurality of fins formed on a semiconductor substrate;
wherein the plurality of fins includes a first fin, the first fin comprising a base portion of the first fin and an upper portion of the first fin, the base portion of the first fin comprising relaxed silicon-germanium (SiGe) and the upper portion of the first fin comprising a first semiconductor material, and
wherein (i) both the upper portion of the first fin and the base portion of the first fin have a substantially similar width and (ii) the upper portion of the first fin is of a thickness that is greater than a thickness of the base portion of the first fin.
2. The FET structure of claim 1 , wherein the plurality of fins further include:
a second fin, the second fin including a base portion of the second fin and an upper portion of the second fin, the base portion of the second fin comprising relaxed silicon-germanium (SiGe) and the upper portion of the second fin comprising a second semiconductor material.
3. The FET structure of claim 1 , wherein the first semiconductor material is strained silicon (Si).
4. The FET structure of claim 2 , wherein the second semiconductor material is high-germanium (high-Ge) content SiGe.
5. The FET structure of claim 1 , wherein the relaxed SiGe is relaxed utilizing a thermal annealing process.
6. The FET structure of claim 1 , wherein the plurality of fins includes a set of fins that are comprised of relaxed silicon (Si).
7. The FET structure of claim 2 , wherein the first semiconductor material and the second semiconductor material are epitaxially grown on the relaxed SiGe.
8. The FET structure of claim 1 , wherein respective side-wall portions of the upper portion of the first fin and the base portion of the first fin are substantially parallel.
9. The FET structure of claim 4 , wherein the first semiconductor material is strained silicon (Si).