Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs
View Patent ↗A method is provided for forming an integrated circuit with an n-region including n-type FinFETs and a p-region including p-type FinFETs. Initially, a silicon-germanium (SiGe) layer consisting essentially of silicon (Si) and germanium (Ge) is formed. The SiGe layer is recessed to form a recessed SiGe layer in the n-type region while leaving an intact SiGe layer in the p-region. A Si layer consisting essentially of Si is formed on the recessed SiGe layer. The Si layer and recessed SiGe layer are patterned to form a Si/SiGe fin comprising a Si fin portion disposed on a recessed SiGe fin portion. The intact SiGe layer in the p-region is patterned to form an intact SiGe fin. The recessed SiGe fin portion in the n-region is selectively oxidized utilizing an oxidation process having an oxidation rate in the recessed SiGe fin portion faster than an oxidation rate in the Si fin portion.
1. A method for forming an integrated circuit with an n-region including n-type FinFETs and a p-region including p-type FinFETs, the method comprising the steps of:
forming a silicon-germanium (SiGe) layer consisting essentially of silicon (Si) and germanium (Ge);
recessing the SiGe layer to form a recessed SiGe layer in the n-region while leaving an intact SiGe layer in the p-region;
forming a Si layer consisting essentially of Si on the recessed SiGe layer in the n-region;
patterning the Si layer and the recessed SiGe layer in the n-region to form a Si/SiGe fin comprising a Si fin portion disposed on a recessed SiGe fin portion;
patterning the intact SiGe layer in the p-region to form an intact SiGe fin; and
selectively oxidizing the recessed SiGe fin portion in the n-region utilizing an oxidation process having an oxidation rate in the recessed SiGe fin portion faster than an oxidation rate in the Si fin portion.
2. The method of claim 1 , wherein the step of forming the SiGe layer comprises oxidizing a layer comprising silicon and germanium.
3. The method of claim 1 , wherein the step of recessing the SiGe layer comprises forming a masking layer covering the p-region and open over the n-region.
4. The method of claim 3 , wherein forming the masking layer comprises photolithography and reactive ion etching.
5. The method of claim 3 , wherein the step of forming the Si layer is performed at least in part with the masking layer in place.
6. The method of claim 1 , wherein the step of forming the Si layer comprises epitaxial growth of silicon on silicon-germanium.
7. The method of claim 1 , wherein the Si layer is tensily strained immediately after formation.
8. The method of claim 1 , wherein the step of selectively oxidizing the SiGe fin portion comprises forming a masking layer covering the p-region and open over the n-region.
9. The method of claim 8 , wherein forming the masking layer comprises photolithography and reactive ion etching.
10. The method of claim 8 , wherein the masking layer is conformal with the intact SiGe fin.
11. The method of claim 8 , wherein the masking layer comprises silicon nitride.
12. The method of claim 1 , wherein the step of selectively oxidizing the SiGe fin portion comprises wet oxidation.
13. The method of claim 1 , wherein the step of selectively oxidizing the SiGe fin portion increases tensile strain in the Si fin portion.
14. The method of claim 1 , wherein the intact SiGe fin in the p-region is compressively strained.