Field effect transistor including strained germanium fins
View Patent ↗In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.
1. A device comprising:
a p-type field effect transistor region including at least one fin comprising compressive strained germanium grown on a sidewall of a mandrel comprising strain relaxed silicon germanium, wherein one end of the at least one fin comprising compressive strained germanium is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the end directly contact the shallow trench isolation layer, and wherein a second side of the end includes a lower portion that directly contacts the strain relaxed silicon germanium and an upper portion that directly contacts the shallow trench isolation layer; and
an n-type field effect transistor region including at least one fin comprising tensile strained germanium.
2. The device of claim 1 , wherein the tensile strained germanium is grown on a sidewall of a mandrel comprising at least one Group III-V semiconductor material.
3. The device of claim 2 , wherein the at least one Group III-V semiconductor material is a strain relaxed Group III-V semiconductor material.
4. The device of claim 3 , wherein one end of the at least one fin comprising tensile strained germanium is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the end directly contact the shallow trench isolation layer.
5. The device of claim 4 , wherein a second side of the end includes a lower portion that directly contacts the strain relaxed Group III-V semiconductor material and an upper portion that directly contacts the shallow trench isolation layer.
6. The device of claim 2 , wherein the at least one Group III-V semiconductor material comprises:
a layer of gallium arsenide; and
a layer of indium gallium arsenide deposited over the layer of gallium arsenide.
7. The device of claim 1 , wherein the device is a finFET.
8. The device of claim 1 , wherein the p-type field effect transistor region and the n-type field effect transistor region are homo-integrated.
9. The device comprising:
a p-type field effect transistor region, comprising:
a first mandrel comprising relaxed silicon germanium; and
a first fin grown on a sidewall of the mandrel and comprising compressive strained germanium, wherein the first fin comprises:
a first end that is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the first end directly contact the shallow trench isolation layer; and
a second side of the first end that includes a lower portion that directly contacts the relaxed silicon germanium and an upper portion that directly contacts the shallow trench isolation layer; and
an n-type field effect transistor region, comprising:
a second mandrel comprising at least one relaxed Group III-V semiconductor material; and
a second fin grown on a sidewall of the second mandrel and comprising tensile strained germanium.
10. The device of claim 9 , wherein the device is a finFET.
11. The device of claim 9 , wherein the p-type field effect transistor region and the n-type field effect transistor region are homo-integrated.
12. The device of claim 9 , wherein the at least one relaxed Group III-V semiconductor material comprises:
a layer of gallium arsenide; and
a layer of indium gallium arsenide deposited over the layer of gallium arsenide.
13. The device of claim 9 , wherein the second fin comprises:
a first end that is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the first end directly contact the shallow trench isolation layer.
14. The device of claim 13 , wherein the second fin further comprises:
a second side of the first end includes a lower portion that directly contacts the relaxed Group III-V semiconductor material and an upper portion that directly contacts the shallow trench isolation layer.
15. A device comprising:
a p-type field effect transistor region including at least one fin comprising compressive strained germanium; and
an n-type field effect transistor region including at least one fin comprising tensile strained germanium grown on a sidewall of a mandrel comprising at least one strain relaxed Group III-V semiconductor material, wherein one end of the at least one fin comprising tensile strained germanium is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the end directly contact the shallow trench isolation layer, and wherein a second side of the end includes a lower portion that directly contacts the strain relaxed Group III-V semiconductor material and an upper portion that directly contacts the shallow trench isolation layer.
16. The device of claim 15 , wherein the compressive strained germanium is grown on a sidewall of a mandrel comprising silicon germanium.
17. The device of claim 16 , wherein the silicon germanium is strain relaxed silicon germanium.
18. The device of claim 17 , wherein one end of the at least one fin comprising compressive strained germanium is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the end directly contact the shallow trench isolation layer.