IP Library Granted Patent US 9,484,264
Granted Patent B1
US 9,484,264 · App. 14/812,330 · Granted Nov 1, 2016

Field effect transistor contacts

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,484,264
App. No.
14/812,330
Granted
Nov 1, 2016
Kind
B1
Abstract

A first field effect transistor (FET) device includes a first gate over a first channel region of a first fin arranged on a substrate, a second gate of a second FET device over a second channel region of a second fin arranged on the substrate, the second channel region having a width that is greater than a width of the first channel region, a first cavity that exposes an active region of the first FET device and a second cavity that exposes an active region of the second FET device, and a conductive material in the first cavity to define a first contact and a conductive material in the second cavity to define a second contact, the second contact having a width that is greater than a width of the first contact.

Claims (12)

1. A field effect transistor device comprising:

a first fin arranged on a substrate;

a second fin arranged on the substrate;

a first gate stack arranged on the first fin;

a second gate stack arranged on the second fin, the first gate stack having a width that is greater than a width of the second gate stack;

a first conductive contact electrically communicative with an active region of the first fin; and

a second conductive contact electrically communicative with an active region of the second fin, the first conductive contact having a width that is greater than a width of the second conductive contact.

2. The device of claim 1 , further comprising an insulator layer arranged between the first conductive contact and the second conductive contact.

3. The device of claim 1 , wherein the first fin includes a semiconductor material.

4. The device of claim 1 , wherein the first conductive contact includes a metallic material.

5. The device of claim 1 , wherein the substrate includes an insulator material.

6. The device of claim 1 , wherein the gate stack includes a metallic gate material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2015
From: BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; STANDAERT, THEODORUS E.; WANG, JUNLI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036210/0098 →