Gate planarity for FinFET using dummy polish stop
A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature.
1. A method for forming a semiconductor device, comprising:
patterning an etch stop feature down to a screen layer in a plurality of regions across the device;
planarizing dummy gate material formed over fins down to the etch stop feature;
planarizing a dielectric fill between gate structures patterned from the dummy gate material down to the etch stop feature; and
planarizing a gate conductor down to the etch stop feature.
2. The method as recited in claim 1 , wherein the etch stop feature includes multiple layers including different materials.
3. The method as recited in claim 1 , wherein the etch stop feature includes a base layer formed from polysilicon or amorphous silicon and an etch stop layer formed on the base layer.
4. The method as recited in claim 3 , further comprising forming electrical components from the base layer.
5. The method as recited in claim 1 , wherein the etch stop layer includes a nitride material.
6. The method as recited in claim 1 , wherein the etch stop feature includes a height configured to preserve a minimum gate height after gate formation processing.
7. The method as recited in claim 1 , wherein the plurality of regions includes regions on the device where gates are not active.
8. The method as recited in claim 1 , further comprising recessing the dielectric layer to expose the fins wherein the dielectric layer forms a shallow trench isolation structure.
9. A method for forming a semiconductor device, comprising:
depositing a dielectric layer over fins formed in a semiconductor substrate, the dielectric layer including a screen layer over tops of the fins;
forming a base layer on the screen layer and an etch stop layer on the base layer;
patterning the etch stop layer and the base layer down to the screen layer in a plurality of regions across the device;
recessing the dielectric layer to expose the fins;
depositing conformal screen dielectric over the fins and the etch stop layer;
depositing dummy gate material;
planarizing the dummy gate material and stopping on the etch stop layer;
patterning gate structures through the dummy gate material;
forming a spacer layer over the gate structures;
filling spaces between the gate structures with a dielectric fill;
recessing the spacers to form divots and expose the dummy gate material;
filling the divots;
planarizing the dielectric fill and the dummy gate material stopping on the etch stop layer;
forming gate stacks including a gate conductor; and
planarizing the gate conductor stopping on the etch stop layer.
10. The method as recited in claim 9 , wherein the base layer includes polysilicon or amorphous silicon.
11. The method as recited in claim 9 , wherein the etch stop layer includes a nitride material.
12. The method as recited in claim 9 , further comprising forming electrical components from the base layer.
13. The method as recited in claim 9 , wherein the etch stop feature includes a height configured to preserve a minimum gate height after gate formation processing.
14. The method as recited in claim 9 , wherein the plurality of regions includes regions on the device where gates are not active.
15. The method as recited in claim 9 , further comprising recessing the dielectric layer to expose the fins wherein the dielectric layer forms a shallow trench isolation structure.
16. The method as recited in claim 9 , wherein the etch stop feature includes multiple layers including different materials.
17. The method as recited in claim 9 , wherein the etch stop feature includes a base layer formed from polysilicon or amorphous silicon and an etch stop layer is formed on the base layer.