Hybrid III-V technology to support multiple supply voltages and off state currents on same chip
View Patent ↗Techniques for forming dual III-V semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one aspect, a method of forming dual III-V semiconductor channel materials on a wafer includes the steps of: providing a wafer having a first III-V semiconductor layer on an oxide; forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer; converting the first III-V semiconductor layer in at least one second active area to an insulator using ion implantation; and removing the second III-V semiconductor layer from at least one first active area selective to the first III-V semiconductor layer.
1. A wafer having dual III-V semiconductor channel materials, the wafer comprising:
at least one first active area defined in the wafer, the at least one first active area comprising a first III-V semiconductor layer disposed directly on an oxide layer; and
at least one second active area defined in the wafer, the at least one second active area comprising i) a portion of the first III-V semiconductor layer having one or more implanted ions selected from the group consisting of: oxygen, iron and chromium, and by way of the implanted ions the portion of the first III-V semiconductor layer present in the at least one second active area is configured to serve as an insulator and ii) a second III-V semiconductor layer disposed directly on the insulator, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer, wherein the second III-V semiconductor layer is absent in the at least one first active area, and wherein the first III-V semiconductor layer in the at least one first active area and the second III-V semiconductor layer in the at least one second active area serve as the dual III-V semiconductor channel materials on the wafer.
2. The wafer of claim 1 , wherein the at least one first active area and the at least one second active area are defined in the wafer using shallow trench isolation.
3. The wafer of claim 1 , wherein the first III-V semiconductor layer comprises a material selected from the group consisting of: aluminum gallium arsenide, aluminum gallium nitride, aluminum indium arsenide, aluminum nitride, gallium antimonide, gallium arsenide, gallium nitride, indium antimonide, indium arsenide, indium gallium arsenide, indium gallium nitride, indium nitride, indium phosphide and combinations comprising at least one of the foregoing materials.
4. The wafer of claim 1 , wherein the second III-V semiconductor layer comprises a material selected from the group consisting of: aluminum gallium arsenide, aluminum gallium nitride, aluminum indium arsenide, aluminum nitride, gallium antimonide, gallium arsenide, gallium nitride, indium antimonide, indium arsenide, indium gallium arsenide, indium gallium nitride, indium nitride, indium phosphide and combinations comprising at least one of the foregoing materials.
5. The wafer of claim 1 , further comprising:
i) at least one first device on the wafer in the at least one first active area and ii) at least one second device on the wafer in the at least one second active area.
6. The wafer of claim 5 , wherein the at least one first device is a transistor having the first III-V semiconductor layer as a semiconductor channel material and the at least one second device is another transistor having the second III-V semiconductor layer as a semiconductor channel material.
7. The wafer of claim 1 , wherein the first III-V semiconductor layer is an only III-V semiconductor channel material in the at least one first active area.
8. The wafer of claim 1 , wherein the second III-V semiconductor layer is an only III-V semiconductor channel material in the at least one second active area.