CMOS fin integration on SOI substrate

1. A method for complementary metal oxide semiconductor (CMOS) fin integration, comprising:

recessing a fin structure buried in a dielectric fill to form a trench in the dielectric fill having a fin portion remaining at a bottom thereof;

epitaxially growing a new fin in the trench from the fin portion, the new fin including SiGe; and

thermally mixing Ge from the SiGe fin into the fin portion remaining at the bottom of the trench.

2. The method as recited in claim 1 , further comprising:

masking the fin structure in a first area while leaving top portions of the fin structures in a second area exposed, wherein the first area includes a region for N-type field effect transistors (NFETs) and the second area includes a region for P-type field effect transistors (PFETs).

3. The method as recited in claim 1 , wherein epitaxially growing the new fin includes epitaxially growing the new fin with a Ge concentration of over 50 atomic %.

4. The method as recited in claim 1 , wherein epitaxially growing the new fin includes epitaxially growing the new fin with a Ge concentration of over 90 atomic %.

5. The method as recited in claim 1 , wherein epitaxially growing the new fin includes epitaxially growing the new fin to a height of at least 30 nm.

6. The method as recited in claim 1 , wherein recessing the fin structure includes recessing the fin structure to between about 5 nm to about 10 nm in height.

7. The method as recited in claim 1 , wherein the trench includes a width of between about 20 nm to about 150 nm.

8. The method as recited in claim 1 , further comprising thermally mixing Ge from the new fin into the fin portion.

9. The method as recited in claim 1 , wherein the step of epitaxially growing is independent of Ge concentration.

10. A method for complementary metal oxide semiconductor (CMOS) fin integration, comprising:

forming fin structures from a silicon layer of a silicon-on-insulator substrate;

forming a dielectric fill between the fin structures;

exposing top portions of the fin structures by removing a portion of the dielectric fill;

recessing the fin structures to form trenches within the dielectric fill, each trench having a silicon portion remaining at a bottom thereof;

epitaxially growing a SiGe fin in the trench from the silicon portion; and

thermally mixing Ge from the SiGe fin into the silicon portion.

11. The method as recited in claim 10 , wherein epitaxially growing the SiGe fin includes epitaxially growing the SiGe fin with a Ge concentration of over 50 atomic %.

12. The method as recited in claim 10 , wherein epitaxially growing the SiGe fin includes epitaxially growing the SiGe fin with a Ge concentration of over 90 atomic %.

13. The method as recited in claim 10 , wherein epitaxially growing the SiGe fin includes epitaxially growing the SiGe fin to a height of at least 30 nm.

14. The method as recited in claim 10 , wherein recessing the fin structures includes recessing the fins to between about 5 nm to about 10 nm in height.

15. The method as recited in claim 10 , wherein the trenches include a width of between about 20 nm to about 150 nm.

16. The method as recited in claim 10 , wherein the step of epitaxially growing is independent of Ge concentration.

17. The method as recited in claim 10 , wherein the SiGe fin is included in a P-type field effect transistor (PFET).