Highly scaled tunnel FET with tight pitch and method to fabricate same
View Patent ↗A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.
1. A method to fabricate a plurality of tunnel field effect transistors (TFETs) comprising:
forming on a surface of a semiconductor substrate a plurality of spaced apart mandrels each having associated spacers; and
processing a pair of the mandrels and the associated spacers to form four adjacent TFETs without requiring use of intervening lithographic processes, where
two adjacent TFETs share a common source or a common drain.
2. The method of claim 1 , where the common source comprises P+ SiGe and where the common drain comprises N+ Si.
3. The method of claim 1 , where a gate structure has a length between the source and the drain in a range of about 10 nm to about 30 nm, where the source has a width in a range of about 10 nm to about 30 nm, and where the drain has a width in a range of about 10 nm to about 30 nm.
4. The method of claim 1 , where a material of the source comprises P+ SiGe doped with boron.
5. The method of claim 1 , where a material of the drain comprises N+ Si doped with phosphorous.
6. The method of claim 1 , where the mandrels are comprised of a dielectric material.
7. The method of claim 1 , where the mandrels are comprised of amorphous carbon (aC).
8. The method of claim 1 , where the source and the drain have opposite doping polarities.
9. The method of claim 1 , where the source and/or the drain comprises a sigma shape configured to impart strain on a channel underlying a gate structure of the TFET.
10. The method of claim 9 , where the source and/or the drain is configured to impart strain on a channel underlying a gate structure of the TFET by anisotropically etching the semiconductor substrate.
11. The method of claim 10 , where anisotropically etching the semiconductor substrate comprises applying a chemical etch to the semiconductor substrate.
12. The method of claim 10 , where anisotropically etching the semiconductor substrate comprises etching in a substantially downward direction into the semiconductor substrate to form a substantially rectangular box-shaped recess and applying tetramethylammonium hydroxide in substantially lateral directions to walls of the substantially rectangular box-shaped recess.
13. The method of claim 12 , where applying tetramethylammonium hydroxide in substantially lateral directions to walls forms non-vertical walls in the substantially rectangular box-shaped recess.