Forming multi-stack nanowires using a common release material
View Patent ↗A method for forming a multi-stack nanowire device includes forming a common release layer on a substrate, the common release layer comprising a common release material. The method also includes forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material, and forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material. The method further includes patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins and forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process.
1. A multi-stack nanowire device comprising:
two or more fins each comprising a multi-layer stack comprising two or more nanowires, wherein portions of the two or more nanowires are doped to form a plurality of source/drain regions;
two or more gates formed over portions of the two or more fins between the plurality of source/drain regions, the gates filling in spaces between the two or more nanowires in each of the fins;
wherein a first one of the two or more fins comprises a multi-layer stack of two or more nanowires of a first material;
wherein a second one of the two or more fins comprises a multi-layer stack of two or more nanowires of a second material different than the first material; and
wherein the first material and the second material are resistant to a given etchant; and
an anchor layer positioned below each end portion of each of the two or more nanowires, wherein each of the two or more nanowires is supported by two anchor layers, and wherein each anchor layer is an insulator material.
2. An integrated circuit comprising:
one or more multi-stack nanowire devices; wherein each of the one or more multi-stack nanowire devices comprises:
two or more fins each comprising a multi-layer stack comprising two or more nanowires, wherein portions of the two or more nanowires are doped to form a plurality of source/drain regions;
two or more gates formed over portions of the two or more fins between the plurality of source/drain regions, the gates filling in spaces between the two or more nanowires in each of the fins;
wherein a first one of the two or more fins comprises a multi-layer stack of two or more nanowires of a first material;
wherein a second one of the two or more fins comprises a multi-layer stack of two or more nanowires of a second material different than the first material; and
wherein the first material and the second material are resistant to a given etchant; and
an anchor layer positioned below each end portion of each of the two or more nanowires, wherein each of the two or more nanowires is supported by two anchor layers, and wherein each anchor layer is an insulator material.
3. The multi-stack nanowire device of claim 1 , wherein the first material comprises silicon and the second material comprises silicon germanium.
4. The multi-stack nanowire device of claim 3 , wherein the given etchant is configured to remove gallium phosphide selective to silicon and silicon germanium.
5. The multi-stack nanowire device of claim 4 , wherein the given etchant comprises a composition of hydrochloric acid, acetic acid and hydrogen peroxide in equal amounts.
6. The multi-stack nanowire device of claim 1 , wherein the first fin comprises an n-channel field-effect transistor multi-layer stack and the second fin comprises a p-channel field-effect transistor multi-layer stack.
7. The multi-stack nanowire device of claim 1 , wherein the first material comprises a first group II-IV material, the second material comprises a second group II-IV material, and the given etchant removes a group III-V material selective to the first group II-IV material and the second group II-IV material.
8. The multi-stack nanowire device of claim 1 , wherein the gates comprise a high-k gate dielectric material comprising at least one of hafnium oxide, zirconium oxide and lanthanum oxide.
9. The multi-stack nanowire device of claim 1 , wherein the gates comprise a work function metal comprising at least one of titanium nitride and tantalum nitride.
10. The multi-stack nanowire device of claim 1 , wherein the gates comprise a gate metal comprising at least one of tungsten and aluminum.
11. The multi-stack nanowire device of claim 1 , further comprising a gate stack comprising the two or more gates and a gate dielectric material in spaces between the two or more fins, the gate stack completely wrapping around one or more of the nanowires in the first fin and one or more nanowires in the second fin.
12. The integrated circuit of claim 2 , wherein the first material comprises silicon and the second material comprises silicon germanium.
13. The integrated circuit of claim 12 , wherein the given etchant is configured to remove gallium phosphide selective to silicon and silicon germanium.
14. The integrated circuit of claim 13 , wherein the given etchant comprises a composition of hydrochloric acid, acetic acid and hydrogen peroxide in equal amounts.
15. The integrated circuit of claim 2 , wherein the first fin comprises an n-channel field-effect transistor multi-layer stack and the second fin comprises a p-channel field-effect transistor multi-layer stack.
16. The integrated circuit of claim 2 , wherein the first material comprises a first group II-IV material, the second material comprises a second group II-IV material, and the given etchant removes a group III-V material selective to the first group II-IV material and the second group II-IV material.
17. The integrated circuit of claim 2 , wherein the gates comprise a high-k gate dielectric material comprising at least one of hafnium oxide, zirconium oxide and lanthanum oxide.
18. The integrated circuit of claim 2 , wherein the gates comprise a work function metal comprising at least one of titanium nitride and tantalum nitride.
19. The integrated circuit of claim 2 , wherein the gates comprise a gate metal comprising at least one of tungsten and aluminum.
20. The integrated circuit of claim 2 , further comprising a gate stack comprising the two or more gates and a gate dielectric material in spaces between the two or more fins, the gate stack completely wrapping around one or more of the nanowires in the first fin and one or more nanowires in the second fin.