IP Library Granted Patent US 9,312,173
Granted Patent B2
US 9,312,173 · App. 14/281,444 · Granted Apr 12, 2016

Self-limiting silicide in highly scaled fin technology

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Quick Facts
Patent No.
US 9,312,173
App. No.
14/281,444
Granted
Apr 12, 2016
Kind
B2
Abstract

A method of forming a metal semiconductor alloy on a fin structure that includes forming a semiconductor material layer of a polycrystalline crystal structure material or amorphous crystal structure material on a fin structure of a single crystal semiconductor material, and forming a metal including layer on the semiconductor material layer. Metal elements from the metal including layer may then be intermixed metal elements with the semiconductor material layer to provide a metal semiconductor alloy contact on the fin structure. A core of the fin structure of the single crystal semiconductor material is substantially free of the metal elements from the metal including layer.

Claims (8)

1. A method of forming a metal semiconductor alloy on a fin structure comprising:

forming a sacrificial gate structure on a channel portion of the fin structure;

forming a semiconductor material layer of a polycrystalline crystal structure material or amorphous crystal structure material on source and drain regions portions of the fin structure that have a single crystal semiconductor material after forming the sacrificial gate structure;

forming a metal including layer on the semiconductor material layer of the polycrystalline crystal structure material or the amorphous crystal structure material;

intermixing metal elements from the metal including layer with the semiconductor material layer to provide a metal semiconductor alloy contact on the fin structure, wherein a core of the fin structure of the single crystal semiconductor material is substantially free of the metal elements from the metal including layer; and

replacing the sacrificial gate structure with a functional gate structure after forming the metal semiconductor alloy contact.

2. The method of claim 1 , wherein the gate structure is a functional gate structure comprising at least one gate dielectric layer and at least one gate conductor layer.

3. The method claim 1 , wherein the functional channel includes at least one gate dielectric layer on the channel portion of the fin structure, and at least one gate conductor on the at least one gate dielectric.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2014
From: CHENG, KANGGUO; DORIS, BRUCE B.; HASHEMI, POUYA; KHAKIFIROOZ, ALI; REZNICEK, ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 032925/0645 →