Forming multi-stack nanowires using a common release material

1. A method comprising:

forming a common release layer on a substrate, the common release layer comprising a common release material;

forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material;

forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material;

patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins; and

forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process;

wherein the first multi-layer stack comprises:

a first layer comprising a first material;

a second layer formed over the first layer, the second layer comprising the common release material; and

a third layer formed over the second layer, the third layer comprising the first material;

wherein the second multi-layer stack comprises:

a fourth layer comprising a second material;

a fifth layer formed over the fourth layer, the fourth layer comprising the common release material; and

a sixth layer formed over the fifth layer, the sixth layer comprising the second material; and

wherein the first material is different than the second material.

2. The method of claim 1 , wherein the common release material is gallium phosphide, the first material is silicon germanium and the second material is silicon.

3. A method comprising:

forming a common release layer on a substrate, the common release layer comprising a common release material;

forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material;

forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material;

patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins; and

forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process;

wherein forming the first multi-layer stack comprises:

depositing an oxide layer on the second portion of the common release layer; and

forming the first multi-stack layer on the first portion of the common release layer.

4. The method of claim 3 , wherein forming the second multi-layer stack comprises:

removing the oxide layer deposited on the second portion of the common release layer;

depositing another oxide layer on the first multi-layer stack; and

forming the second multi-layer stack on the second portion of the common release layer.

5. The method of claim 1 , wherein patterning each of the first multi-layer stack and the second multi-layer stack comprises utilizing a hard mask formed over portions of the first multi-layer stack and the second multi-layer stack.

6. The method of claim 5 , further comprising:

depositing an anchor layer at ends of each of the one or more fins; and

removing the common release material on the substrate, in the first multi-layer stack and in the second multi-layer stack.

7. The method of claim 6 , further comprising depositing an oxide in one or more spaces formed by removal of the common release material.

8. The method of claim 7 , further comprising:

removing the hard mask formed over portions of the first and second multi-layer stack; and

forming a plurality of dummy gates on portions of the two or more multi-stack nanowires.

9. The method of claim 8 , further comprising forming thin spacers on sides of each of the plurality of dummy gates.

10. The method of claim 9 , further comprising:

selectively removing a first portion of the oxide in regions between the two or more multi-stack nanowires not covered by the plurality of dummy gates and in regions between the two or more multi-stack nanowires and the substrate not covered by the plurality of dummy gates; and

depositing a thin spacer to fill in one or more spaces left by removal of the first portion of the oxide.

11. The method of claim 10 , further comprising forming source/drain regions by doping portions of the two or more multi-stack nanowires not covered by the plurality of dummy gates.

12. A method comprising:

forming a common release layer on a substrate, the common release layer comprising a common release material;

forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material;

forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material;

patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins;

forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process;

wherein patterning each of the first multi-layer stack and the second multi-layer stack comprises utilizing a hard mask formed over portions of the first multi-layer stack and the second multi-layer stack;

depositing an anchor layer at ends of each of the one or more fins;

removing the common release material on the substrate, in the first multi-layer stack and in the second multi-layer stack;

depositing an oxide in one or more spaces formed by removal of the common release material;

removing the hard mask formed over portions of the first and second multi-layer stack;

forming a plurality of dummy gates on portions of the two or more multi-stack nanowires;

forming thin spacers on sides of each of the plurality of dummy gates;

selectively removing a first portion of the oxide in regions between the two or more multi-stack nanowires not covered by the plurality of dummy gates and in regions between the two or more multi-stack nanowires and the substrate not covered by the plurality of dummy gates;

depositing a thin spacer to fill in one or more spaces left by removal of the first portion of the oxide; and

forming source/drain regions by doping portions of the two or more multi-stack nanowires not covered by the plurality of dummy gates;

wherein n-type doping is used for forming source/drain regions in portions of the two or more multi-stack nanowires in the one or more fins patterned from the first multi-layer stack and wherein p-type doping is used for forming source/drain regions in portions of the two or more multi-stack nanowires in the one or more fins patterned from the second multi-layer stack.

13. The method of claim 11 , further comprising:

forming an insulator in spaces between the plurality of dummy gates and above the source/drain regions;

planarizing the top surface of the insulator; and

removing the plurality of dummy gates.

14. The method of claim 13 , further comprising removing a second portion of the oxide in regions between the two or more multi-stack nanowires not covered by the insulator.

15. The method of claim 14 , further comprising forming a gate stack by depositing a gate material to fill in spaces surrounding the two or more multi-stack nanowires, wherein the gate stack is completely wrapped around the two or more multi-stack nanowires.

16. The method of claim 15 , further comprising depositing a gate cap onto the gate stack.