Porous silicon relaxation medium for dislocation free CMOS devices
View Patent ↗A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
1. A method for forming complementary metal oxide semiconductor devices, comprising:
doping a second portion of a tensile-strained silicon layer outside a first portion to form a doped portion;
growing an undoped silicon layer on the doped portion;
relaxing strain in the undoped silicon layer over the doped portion by converting the doped portion to an oxide to form a relaxed layer;
growing a SiGe layer on the relaxed layer;
oxidizing the SiGe layer to convert the relaxed layer to a compressed SiGe layer; and
etching fins from the tensile-strained silicon layer and the compressed SiGe layer.
2. The method as recited in claim 1 , wherein doping the second portion of the tensile-strained silicon layer includes boron doping the second portion.
3. The method as recited in claim 1 , wherein converting the doped portion to an oxide to form a relaxed layer includes converting the doped portion to a porous silicon then converting the porous silicon to the oxide.
4. The method as recited in claim 3 , wherein converting the doped portion to a porous silicon includes converting the doped portion to the porous silicon with a porosity of at least 50%.
5. The method as recited in claim 1 , wherein oxidizing the SiGe layer to convert the relaxed silicon layer to a compressed SiGe layer includes employing a condensation process to form the compressed SiGe layer.
6. The method as recited in claim 1 , further comprising forming N-type field effect transistors from the fins formed from the tensile-strained silicon layer and forming P-type field effect transistors from the fins formed from the compressed SiGe layer.
7. The method as recited in claim 6 , wherein the N-type field effect transistors and the P-type field effect transistors have different heights and the method further comprises adjusting the heights to adjust N/P ratio.
8. The method as recited in claim 1 , wherein relaxing strain in the undoped silicon layer includes relaxing strain by at least 50%.
9. The method as recited in claim 1 , wherein converting the doped portion to a porous silicon to form a relaxed silicon layer includes anodizing the doped portion.
10. The method as recited in claim 1 , further comprising removing a hard mask.