Highly scaled tunnel FET with tight pitch and method to fabricate same

1. A structure, comprising:

a substrate; and

a tunnel field effect transistor (TFET) comprised of

a source region disposed in the substrate and having an overlying source contact, the source region comprised of first semiconductor material having a first doping type,

a drain region disposed in the substrate and having an overlying drain contact, the drain region comprised of second semiconductor material having a second doping type opposite the first doping type, and

a gate structure that overlies a channel region disposed between the source region and the drain region;

where the source region and the drain region are asymmetric with respect to one another and one of the source region and the drain region contains a larger volume of semiconductor material than the other one of the source region and drain region;

where the gate structure comprises,

a first wall comprising a gate dielectric material,

a second wall comprising the gate dielectric material, the second wall spaced from the first wall,

a third wall comprising the gate dielectric material, the third wall being positioned on the substrate between the first wall and the second wall, and

a gate fill disposed between the first wall, the second wall, and the third wall.

2. The structure of claim 1 , where the source region has a plurality of non-vertical sidewalls configured, with the first semiconductor material, to apply stress to an adjacent region of the semiconductor substrate wherein the channel region is located.

3. The structure of claim 1 , where the first semiconductor material comprises SiGe doped with boron.

4. The structure of claim 3 , where the boron is present in a concentration of about 10 18 atoms/cm 2 to about 10 21 atoms/cm 2 .

5. The structure of claim 1 , where the second semiconductor material comprises Si doped with phosphorous.

6. The structure of claim 5 , where the phosphorous is present in a concentration of about 10 18 atoms/cm 2 to about 10 21 atoms/cm 2 .

7. The structure of claim 1 , where the gate structure has a length between the source region and the drain region in a range of about 10 nm to about 30 nm, where the source region has a width in a range of about 10 nm to about 30 nm, and where the drain region has a width in a range of about 10 nm to about 30 nm.

8. The structure of claim 1 , where a gate length of the TFET is in a range of about 10 nm to about 30 nm.

9. The structure of claim 1 , where the substrate comprises silicon.

10. The structure of claim 1 , where the gate dielectric material comprises a high k dielectric material.

11. The structure of claim 10 , where the high k dielectric material comprises HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate of any of the foregoing materials, or an alloy of any of the foregoing materials.

12. The structure of claim 1 , where the gate fill comprises TiN, TiC, TaN, TaC, TaSiN, HfN, W, Al, Ru, or a combination of any of the foregoing materials.

13. The structure of claim 1 , further comprising a source contact disposed on the source region and a drain contact disposed on the drain region.

14. The structure of claim 13 , where the source contact and the drain contact each comprise a metal.

15. The structure of claim 14 , where the metal for the source contact and the drain contact each comprise Al, TiN, or W.