Adjacent strained <100> NFET fins and <110> PFET fins
The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming strained <100> n-channel field effect transistor (NFET) fins and adjacent strained <110> p-channel field effect transistor (PFET) fins on the same substrate. A <110> crystalline oxide layer may be either bonded or epitaxially grown on a substrate layer. A first SOI layer with a <100> crystallographic orientation and tensile strain may be bonded to the crystalline oxide layer. A second SOI layer with a <110> crystallographic orientation and compressive strain may be epitaxially grown on the crystalline oxide layer. The first SOI layer may be used to form the fins of a NFET device. The second SOI layer may be used to form the fins of a PFET device.
1. A method comprising:
forming a crystalline oxide layer directly on an upper surface of a substrate, the crystalline oxide layer comprising a oxide material having a crystallographic orientation <110>;
forming a first silicon on insulator (SOI) layer on an upper surface of the crystalline oxide layer, the first SOI layer comprising a semiconductor material having a crystallographic orientation <100>;
removing a portion of the first SOI layer to form an opening, the opening exposing the upper surface of the crystalline oxide layer and creating a first remaining portion of the first SOI layer and a second remaining portion of the first SOI layer;
forming a hardmask on an upper surface of the first remaining portion of the first SOI layer;
removing the second remaining portion of the first SOI layer exposing the upper surface of the crystalline oxide layer;
forming a second silicon on insulator (SOI) layer directly on an upper surface of the crystalline oxide layer adjacent to the first SOI layer, the second SOI layer comprising a semiconductor material having a crystallographic orientation <110>;
removing the hardmask;
forming <100> fins in the first SOI layer; and
forming <110> fins in the second SOI layer.
2. The method of claim 1 , wherein the forming the crystalline oxide layer on the substrate comprises epitaxially growing the crystalline oxide layer on the substrate.
3. The method of claim 1 , wherein the forming the crystalline oxide layer on the substrate comprises wafer bonding and splitting.
4. The method of claim 1 , wherein the forming the first SOI layer on the crystalline oxide layer comprises wafer bonding and splitting.
5. The method of claim 1 , wherein the forming the second SOI layer on the crystalline oxide layer comprises epitaxially growing the second SOI layer on the crystalline oxide layer.
6. The method of claim 1 , wherein the first SOI layer comprises strained silicon.
7. The method of claim 1 , wherein the second SOI layer comprises strained silicon germanium.
8. The method of claim 1 , wherein the substrate comprises silicon having a crystallographic orientation <100>.
9. The method of claim 1 , wherein the substrate comprises silicon having a crystallographic orientation <110>.
10. A structure comprising:
a crystalline oxide layer on an upper surface of a substrate, the crystalline oxide layer comprising a oxide material having a crystallographic orientation <110>;
<100> fins directly on an upper surface of the crystalline oxide layer, the <100> fins comprising a first silicon on insulator (SOI) layer made of a semiconductor material having a crystallographic orientation <100>;
a shallow trench isolation (STI) layer on the upper surface of the crystalline oxide layer adjacent to the <100> fins; and
<110> fins directly on the upper surface of the crystalline oxide layer adjacent to the STI layer, the <110> fins comprising a second silicon on insulator (SOI) layer made of a semiconductor material having a crystallographic orientation <110>.
11. The structure of claim 10 , wherein the first SOI layer comprises tensile strained silicon.
12. The structure of claim 10 , wherein the second SOI layer comprises a compressive strained silicon germanium.