Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy
View Patent ↗A method of making a semiconductor device includes forming a gate covered by a hard mask over a substrate; disposing a mask over the gate and the hard mask; patterning the mask to expose a portion of the gate and the hard mask; cutting the gate and hard mask to form two shorter gates, each of the two shorter gates having an exposed end portion; undercutting the exposed end portion of at least one of the two shorter gates to form an overhanging hard mask portion over the exposed end portion; and forming spacers along a gate sidewall and beneath the overhanging hard mask portion.
1. A semiconductor device, comprising:
a gate disposed over a substrate, the gate having a longitudinal axis defining a length of the gate, a transverse axis defining a width of the gate, and a first distal end and a second distal end arranged at opposing ends of the gate on the longitudinal axis of the gate, the length of the gate being greater than the width of the gate; and
a hard mask disposed over the gate, the hard mask having a longitudinal axis defining a length of the hard mask, a transverse axis defining a width of the hard mask, and a first distal end and a second distal end arranged at opposing ends of the hard mask on the longitudinal axis of the hard mask, the length of the hard mask being greater than the width of the hard mask, and the hard mask comprising an insulating material;
wherein the width of the gate and the hard mask are substantially the same, the length of the hard mask is greater than the length of the gate, and the hard mask has a first overhang region arranged over the first distal end of the gate and a second overhang region arranged over the second distal end of the gate; and
wherein the gate comprises a polysilicon material or an amorphous silicon material that extends continuously from the substrate to the hard mask.
2. The semiconductor device of claim 1 , wherein the first overhang region or the second overhang region has a width in a range from about 3 to about 30 nm.
3. The semiconductor device of claim 1 , further comprising gate spacers disposed beneath the first overhang region and the second overhang region.
4. The semiconductor device of claim 3 , wherein the gate spacer has a thickness in a range from about 3 to about 30 nm.
5. The semiconductor device of claim 3 , wherein the gate spacer is SiO2, SiN, SiBN, SiCN, SiBCN, or any combination thereof.
6. The semiconductor device of claim 1 , wherein gate comprises a replacement gate material.