Techniques for multiple gate workfunctions for a nanowire CMOS technology
In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a wafer, wherein the nanowires are suspended at varying heights above an oxide layer of the wafer; and forming gate stacks of the transistors at least partially surrounding portions of each of the nanowires by: i) depositing a conformal gate dielectric around the nanowires and on the wafer beneath the nanowires; ii) depositing a conformal workfunction metal on the conformal gate dielectric around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is varied based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) depositing a conformal poly-silicon layer on the conformal workfunction metal around the nanowires and on the wafer beneath the nanowires.
1. A complementary metal oxide semiconductor (CMOS) device comprising multiple nanowire-based transistors having different threshold voltages, comprising:
a wafer comprising an oxide layer on a substrate;
nanowires and pads on the wafer, wherein the pads are attached to opposite ends of the nanowires and anchor the nanowires to the wafer, and wherein the nanowires are suspended at varying heights above the oxide layer; and
gate stacks of the nanowire-based transistors at least partially surrounding portions of each of the nanowires, the gate stacks comprising i) a conformal gate dielectric both around the nanowires and on the wafer beneath the nanowires; ii) a conformal workfunction metal on the conformal gate dielectric both around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) a conformal poly-silicon layer on the conformal workfunction metal both around the nanowires and on the wafer beneath the nanowires,
wherein the portions of the nanowires at least partially surrounded by the gate stacks serve as channel regions of the nanowire-based transistors, wherein portions of the nanowires extending out from the gate stacks and the pads serve as source and drain regions of the nanowire-based transistors, and wherein the nanowire-based transistors have different threshold voltages based on the varied amount of the conformal workfunction metal deposited around the nanowires.
2. The CMOS device of claim 1 , further comprising:
a conformal oxide layer at an interface between the conformal gate dielectric and the nanowires.
3. The CMOS device of claim 1 , wherein the wafer further comprises a SOI layer on a side of the oxide layer opposite the substrate, and wherein the SOI layer is present beneath the pads.
4. The CMOS device of claim 1 , wherein the oxide layer is recessed at varying depths beneath the nanowires.
5. The CMOS device of claim 1 , wherein the conformal workfunction metal comprises an n-type workfunction metal selected from the group consisting of lanthanum, titanium, and tantalum.
6. The CMOS device of claim 1 , wherein the conformal workfunction metal comprises a p-type workfunction metal selected from the group consisting of aluminum, dysprosium, gadolinium, and ytterbium.