High germanium content FinFET devices having the same contact material for nFET and pFET devices
View Patent ↗FinFET structures are formed on silicon germanium fins having high germanium content. Silicon germanium source/drain regions formed in fin recesses in nFET regions are provided with arsenic or phosphorus-doped germanium caps. Uniform tensile strain is obtained through the use of ungraded silicon germanium in the n-type source/drain regions. Location of the germanium caps above the fin structure ensures they have no materially negative impact on strain. Boron doped germanium source/drain regions are formed in fin recesses in pFET regions and provide for compressive strain. Contact formation using the same material in both nFET and pFET regions of the same substrate facilitates fabrication.
1. A method comprising:
obtaining a structure comprising a substrate, a plurality of rows of parallel semiconductor fins on the substrate, the semiconductor fins having the composition Si 1-x Ge x where x is 0.85 or greater, a plurality of parallel gate structures on the substrate and extending across the rows of parallel semiconductor fins, and a plurality of spacers on the parallel gate structures, the structure having an nFET region and a pFET region;
forming recesses within the semiconductor fins in the nFET and pFET regions;
epitaxially growing n-doped silicon germanium source/drain regions in the recesses within the nFET region;
depositing n-doped cap layers of substantially pure germanium on the n-doped silicon germanium source/drain regions such that the n-doped cap layers extend above the recesses;
epitaxially growing p-doped source/drain regions of substantially pure germanium in the recesses within the pFET region, and
forming a metal contact layer directly on the n-doped, substantially pure germanium cap layers and the p-doped, substantially pure germanium source/drain regions.
2. The method of claim 1 , wherein the n-doped silicon germanium source/drain regions are ungraded.
3. The method of claim 1 , wherein the step of forming the recesses further includes etching partially through the semiconductor fins.
4. The method of claim 3 , wherein the n-doped silicon germanium source/drain regions consist essentially of ungraded Si 1-y Ge y where y is less than x.
5. The method of claim 4 , wherein the substrate comprises monocrystalline silicon.
6. The method of claim 4 , wherein the n-doped, substantially pure germanium cap layers are doped with arsenic or phosphorus.
7. The method of claim 4 , wherein the p-doped, substantially pure germanium source/drain regions are doped with boron.
8. The method of claim 4 , wherein:
the step of epitaxially growing the n-doped silicon germanium source/drain regions further includes growing the n-doped silicon germanium source/drain regions above the recesses.
9. The method of claim 8 , wherein:
the step of epitaxially growing the p-doped, substantially pure germanium source/drain regions further includes growing p-doped, substantially pure germanium cap regions of the p-doped, pure germanium source/drain regions above the recesses.
10. The method of claim 9 , wherein the n-doped, substantially pure germanium cap layers are doped with phosphorus or arsenic and the p-doped, substantially pure germanium source/drain regions are doped with boron.
11. The method of claim 10 , wherein the metal contact layer is formed simultaneously on the n-doped, pure germanium cap layers and the p-doped, substantially pure germanium cap regions of the p-doped, substantially pure germanium source/drain regions.
12. The method of claim 10 , wherein the n-doped, substantially pure germanium cap layers are deposited entirely above the recesses within the semiconductor fins.
13. A semiconductor structure comprising:
a substrate;
a plurality of rows of parallel semiconductor fins on the substrate, the semiconductor fins having the composition Si 1-x Ge x where x is 0.85 or greater
a plurality of parallel gate structures on the substrate and extending across the rows of parallel semiconductor fins;
a plurality of channel regions beneath the gate structures;
a plurality of spacers on the parallel gate structures;
a plurality of recesses within the semiconductor fins, the recesses adjoining the channel regions;
an nFET region including a plurality of n-doped silicon germanium source/drain regions in the recesses and adjoining a plurality of the channel regions;
a plurality of n-doped, substantially pure germanium caps on the n-doped silicon germanium source/drain regions and extending above the recesses;
a pFET region including a plurality of p-doped, substantially pure germanium source/drain regions in the recesses, and
a metal contact layer directly contacting the n-doped, substantially pure germanium caps and the p-doped, substantially pure germanium source/drain regions.
14. The semiconductor structure of claim 13 , wherein the n-doped silicon germanium source/drain regions are ungraded.
15. The semiconductor structure of claim 14 , wherein the n-doped silicon germanium source/drain regions consist essentially of ungraded Si 1-y Ge y where y is less than x.
16. The semiconductor structure of claim 15 , wherein the n-doped, substantially pure germanium caps are doped with phosphorus or arsenic.
17. The semiconductor structure of claim 16 , wherein the recesses extend partially through the semiconductor fins and the n-doped, substantially pure germanium caps are positioned entirely above the recesses within the semiconductor fins.
18. The semiconductor structure of claim 17 , wherein the p-doped, substantially pure germanium source/drain regions include substantially pure germanium cap regions that extend above the recesses and are doped with boron.
19. The semiconductor structure of claim 18 , wherein the metal contact layer consists essentially of a single material.
20. The semiconductor structure of claim 19 , wherein the metal contact layer is selected from the group consisting of nickel, titanium, titanium nitride and tungsten.