SiGe finFET with improved junction doping control
View Patent ↗A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer.
1. A method for fabricating a semiconductor device, the method comprising:
providing a FinFET having a source/drain region and at least one SiGe fin, wherein the at least one SiGe fin has sidewalls and is formed on a silicon substrate layer, a local oxide layer is formed on the silicon substrate layer, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and a plurality of sidewall spacer layers;
recessing the at least one SiGe fin in the source/drain region, wherein the at least one SiGe fin is recessed to the plurality of sidewall spacer layers and the silicon substrate layer;
recessing the local oxide layer in the source/drain region, wherein the local oxide layer is recessed to the plurality of sidewall spacer layers and the silicon substrate layer;
growing an n-doped silicon layer having a thickness between 10 and 30 nm on the silicon substrate layer in the source/drain region, wherein growing an n-doped silicon layer on the silicon substrate layer comprises etching the n-doped silicon layer with an HCl etch from the at least one SiGe fin sidewalls;
etching under the plurality of sidewall spacer layers and the gate structure;
growing either a p-doped silicon layer or a p-doped SiGe layer having a thickness between 40 and 50 nm on the n-doped silicon layer in the source/drain region using tetrasilane or trisilane at a temperature of about 550° C., wherein the p-doped silicon layer or the p-doped SiGe layer comprises boron at a concentration of about 1019 atoms/cm3; and
forming a silicide layer on the p-doped silicon layer or the p-doped SiGe layer in the source/drain region.