CMOS compatible fuse or resistor using self-aligned contacts

1. A semiconductor device, comprising:

dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween;

a trench silicide structure formed in the gap directly on the dielectric layer, the trench silicide structure forming a resistive element; and

self-aligned contacts formed through an interlevel dielectric layer and landing on the trench silicide structure.

2. The device as recited in claim 1 , wherein the trench silicide structures are concurrently formed in active regions for active field effect transistors as a source/drain contact.

3. The device as recited in claim 2 , wherein the self-aligned contacts are concurrently formed in the active regions as a contact to the source/drain contact.

4. The device as recited in claim 1 , wherein the dummy gate structures include a gate conductor, a gate dielectric and sidewall spacers as concurrently formed in active regions for active field effect transistors.

5. The device as recited in claim 1 , wherein the resistive element includes a fuse.

6. The device as recited in claim 1 , wherein the resistive element includes a resistor.

7. The device as recited in claim 1 , wherein the self-aligned contacts wrap-around a sidewall portion of the trench silicide structure.

8. The device as recited in claim 1 , wherein the resistive element includes a vertical plane disposed transversely with the substrate between the dummy gate structures.

9. A semiconductor device, comprising:

first gate structures and second gate structures formed on a dielectric layer over a substrate;

a trench silicide structure formed between the first gate structures and between the second gate structures, the trench silicide structure forming a contact to a source/drain region and the trench silicide structure forming a resistor on the dielectric layer; and

self-aligned contacts formed through an interlevel dielectric layer and landing on the trench silicide structure.

10. The device as recited in claim 9 , wherein end portions of the trench silicide structure extend longitudinally beyond a gap formed between the second gate structures.

11. The device as recited in claim 9 , wherein the first and second gate structures include a gate conductor, a gate dielectric and sidewall spacers.

12. The device as recited in claim 9 , wherein the resistor includes a fuse.

13. The device as recited in claim 9 , wherein the second gate structures are formed on the dielectric layer over the substrate outside of an active area.

14. The device as recited in claim 9 , wherein the self-aligned contacts wrap-around a sidewall portion of the trench silicide structure.

15. The device as recited in claim 9 , wherein the resistor includes a vertical plane disposed transversely with the substrate between adjacent second gate structures.

16. A method for fabricating a resistive element on a semiconductor device, comprising:

forming dummy gate structures on a dielectric layer over a substrate with a gap therebetween;

forming a trench silicide structure in the gap directly on the dielectric layer, the trench silicide structure forming a resistive element; and

forming self-aligned contacts through an interlevel dielectric layer and landing on the trench silicide structure.

17. The method as recited in claim 16 , wherein the dummy gate structures, the trench silicide structure and the self-aligned contacts are concurrently formed with corresponding elements in active regions for active field effect transistors.

18. The method as recited in claim 16 , wherein the resistive element includes one of a fuse or a resistor.

19. The method as recited in claim 16 , further comprising wrapping the self-aligned contacts around a sidewall portion of the trench silicide structure.

20. The method as recited in claim 16 , wherein the resistive element includes a vertical plane disposed transversely with the substrate between the dummy gate structures.