Method and structure for forming dually strained silicon
View Patent ↗A semiconductor structure and method for fabricating such. The semiconductor structure includes a monolithic substrate, a first dielectric layer carried by the monolithic substrate and a second dielectric layer carried by the monolithic substrate. The first dielectric layer has a first Young's modulus, and the second dielectric layer has a second Young's modulus. The first Young's modulus is at least twice the second Young's modulus. A compressive SiGe layer is positioned over and in contact with the first dielectric layer. A relaxed SiGe layer is positioned over and in contact with the second dielectric layer. The relaxed SiGe layer is spaced apart from the compressive SiGe layer.
1. A semiconductor structure comprising:
a monolithic substrate;
a first dielectric layer with a first Young's modulus carried by the monolithic substrate;
a second dielectric layer with a second Young's modulus carried by the monolithic substrate, the second dielectric layer positioned lateral to the first dielectric layer, the first Young's modulus is at least twice the second Young's modulus;
a compressive SiGe layer positioned over and in contact with the first dielectric layer; and
a relaxed SiGe layer positioned over and in contact with the second dielectric layer, the relaxed SiGe layer spaced apart from the compressive SiGe layer.
2. The semiconductor structure of claim 1 , further comprising a tensile Si layer positioned over and in contact with the relaxed SiGe layer, the tensile Si layer spaced apart from the compressive SiGe layer.
3. The semiconductor structure of claim 2 , further comprising:
an n-channel field-effect transistor (NFET) at the tensile Si layer; and
a p-channel field-effect transistor (PFET) at the compressive SiGe layer.
4. The semiconductor structure of claim 1 , wherein the first dielectric layer is composed of a different material than the second dielectric layer.
5. The semiconductor structure of claim 1 , wherein the first dielectric layer is a nitride material and the second dielectric layer is an oxide material.
6. The semiconductor structure of claim 5 , wherein the first dielectric layer is silicon nitride (Si 3 N 4 ) and the second dielectric layer is borophosphosilicate glass (BPSG).
7. The semiconductor structure of claim 1 , wherein the first Young's modulus is greater than 200 GPa and the second Young's modulus is less than 100 GPa.
8. The semiconductor structure of claim 1 , further comprising a dielectric divider positioned between the relaxed SiGe layer and the compressive SiGe layer.
9. A method for fabricating a semiconductor structure, the method comprising:
depositing a first dielectric layer with a first Young's modulus over a substrate;
depositing a second dielectric layer with a second Young's modulus over the monolithic substrate lateral to the first dielectric layer, the first Young's modulus is at least twice the second Young's modulus;
bonding a compressed SiGe layer to the first dielectric layer and the second dielectric layer; and
annealing the semiconductor structure such that a first region of the SiGe layer over the first dielectric layer remains the compressed SiGe layer and a second region of the SiGe layer over the second dielectric layer forms a relaxed SiGe layer.
10. The method of claim 9 , further comprising growing an epitaxial Si layer over the relaxed SiGe layer to form a tensile Si layer in contact with the relaxed SiGe layer.
11. The method of claim 10 , further comprising:
forming an n-channel field-effect transistor (NFET) at the tensile Si layer; and
forming a p-channel field-effect transistor (PFET) at the compressive SiGe layer.
12. The method of claim 9 , further comprising etching the SiGe layer before annealing the semiconductor structure such that the first region of the SiGe layer over the first dielectric layer is spaced apart from the second region of the SiGe layer over the second dielectric layer by a separation region.
13. The method of claim 12 , further comprising depositing a dielectric material in the separation region.
14. The method of claim 9 , wherein the first dielectric layer is composed of a different material than the second dielectric layer.
15. The method of claim 9 , wherein the first dielectric layer is a nitride material and the second dielectric layer is an oxide material.
16. The method of claim 9 , wherein the first dielectric layer is silicon nitride (Si 3 N 4 ) and the second dielectric layer is borophosphosilicate glass (BPSG).
17. The method of claim 9 , wherein the first Young's modulus is greater than 200 GPa and the second Young's modulus is less than 100 GPa.
18. A method for fabricating a semiconductor structure, the method comprising:
depositing a first dielectric layer with a first Young's modulus over a substrate;
depositing a second dielectric layer with a second Young's modulus over the monolithic substrate lateral to the first dielectric layer, the second Young's modulus is a least twice the first Young's modulus;
bonding a compressed SiGe layer to the first dielectric layer and the second dielectric layer; and
annealing the semiconductor structure such that a first region of the SiGe layer over the first dielectric layer forms a relaxed SiGe layer.
19. The method of claim 18 , further comprising etching the SiGe layer before annealing the semiconductor structure such that the first region of the SiGe layer over the first dielectric layer is spaced apart from a second region of the SiGe layer over the second dielectric layer by a separation region.
20. The method of claim 18 , further comprising growing an epitaxial Si layer over the relaxed SiGe layer to form a tensile Si layer in contact with the relaxed SiGe layer.