Multiple V

1. A method of forming a multiple threshold voltage (V T ) device structure, the method comprising the steps of:

forming an alternating series of channel layers and barrier layers as a stack on a side of a buried oxide (BOX) opposite a substrate, wherein the stack comprises at least one first channel layer present over at least one first barrier layer, and at least one second channel layer present below the at least one first barrier layer, wherein the at least one first channel layer comprises a first III-V material and the at least one second channel layer comprises a second III-V material, and wherein the first III-V material has a different electron affinity from the second III-V material;

defining at least one first active area and at least one second active area in the stack;

selectively removing the at least one first channel layer and the at least one first barrier layer from the at least one second active area, such that the at least one first channel layer is a top-most layer in the stack in the at least one first active area, and the at least one second channel layer is a top-most layer in the stack in the at least one second active area, wherein the at least one first barrier layer is configured to confine charge carriers to the at least one first channel layer in the first active area; and

forming at least one first gate on the at least one first channel layer in the at least one first active area, and at least one second gate on the at least one second channel layer in the at least one second active area, wherein the at least one first channel layer serves as a channel of a first field effect transistor (FET) in the at least one first active area, and the at least one second channel layer serves as a channel of a second FET in the at least one second active area, and wherein the first FET has a different V T from the second FET based on the different electron affinity between the first III-V material and the second III-V material.

2. The method of claim 1 , wherein the at least one first barrier layer comprises a wider band gap III-V material than the first III-V material.

3. The method of claim 1 , wherein the least one first active area and the at least one second active area are defined in the stack using shallow trench isolation (STI) comprising an STI oxide material which extends completely through each of the channel layers in the stack and down to the BOX.

4. The method of claim 1 , wherein the at least one first channel layer and the at least one first barrier layer are selectively removed from the at least one second active area using a two-step etching process comprising:

using a first etch to remove the at least one first channel layer from the at least one second active area, wherein the at least one barrier layer serves as an etch stop during the first etch; and

using a second etch to remove the at least one first barrier layer from the at least one second active area, wherein the at least one second channel layer serves as an etch stop during the second etch.

5. The method of claim 1 , wherein the at least one first gate and the at least one second gate each both comprise a gate dielectric, a gate metal layer on the gate dielectric, and a semiconductor gate layer on a side of the gate metal layer opposite the gate dielectric.

6. The method of claim 5 , wherein the gate metal layer comprises a same gate metal in both the at least one first gate and the at least one second gate.

7. The method of claim 1 , further comprising the steps of:

forming spacers on opposite sides of the at least one first gate and on opposite sides of the at least one second gate; and

forming raised source and drain regions on the at least one first channel layer on opposite sides of the at least one first gate, and on the at least one second channel layer on opposite sides of the at least one second gate.

8. The method of claim 7 , further comprising the step of:

forming contacts to the raised source and drain regions.

9. The method of claim 1 , wherein the stack further comprises at least one second barrier layer below the at least one second channel layer and at least one third channel layer below the at least one second barrier layer, wherein the at least one third channel layer comprises a third III-V material, and wherein the third III-V material has a different electron affinity from both the first III-V material and the second III-V material.

10. The method of claim 9 , further comprising the steps of:

defining at least one third active area in the stack; and

selectively removing the at least one first channel layer, the at least one first barrier layer, the at least one second channel layer, and the at least one second barrier layer from the at least one third active area, such that the at least one third channel layer is a top-most layer in the stack in the at least one third active area, wherein the at least one second barrier layer is configured to confine charge carriers to the at least one third channel layer in the third active area.

11. The method of claim 10 , further comprising the step of:

forming at least one third gate on the at least one third channel layer in the at least one third active area, wherein the at least one third channel layer serves as a channel of a third FET in the at least one third active area, and wherein the third FET has a different V T from both the first FET and the second FET based on the different electron affinity between the first III-V material, the second III-V material, and the third III-V material.