Finfet devices with multiple channel lengths
View Patent ↗A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second segment, and forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.
1. A method comprising:
patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an oblique angle relative to the second segment, and the continuous fin comprises a substantially uniform width along its entire length, wherein a common vertical plane bisects the first segment of the continuous fin and a third segment of one of a plurality of continuous fins; and
forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin, wherein the common vertical plane is perpendicular to the first gate and the second gate.
2. The method of claim 1 , wherein the continuous fin further comprises a third segment and a third gate substantially covering sides and a top of a portion of the third segment, the third segment is parallel to the first segment and arranged at the oblique angle relative to the second segment, the third gate is substantially parallel to both the first gate and the second gate, and the second segment is parallel to another segment of an adjacent continuous fin.
3. The method of claim 1 , wherein the first gate is substantially perpendicular to the first segment of the continuous fin.
4. The method of claim 1 , wherein the angle between the first segment and the second segment is greater than 90 degrees.
5. The method of claim 1 , wherein a width of the continuous fin is sublithographic in dimension.
6. The method of claim 1 , wherein a length of the portion of the second segment covered by the second gate is greater than a length of the portion of the first segment covered by the first gate, the lengths being measured between opposite sides of the first and second gates.
7. The method of claim 1 , further comprising:
forming an array of transistors from the continuous fin and the first and second gates.
8. A method comprising:
patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an oblique angle relative to the second segment, the first segment and the second segment have a common width along their entire length, and sidewalls of the first segment are coplanar with sidewalls of another segment of an adjacent fin, wherein a common vertical plane bisects the first segment of the continuous fin and a third segment of one of a plurality of continuous fins; and
forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin, wherein the common vertical plane is perpendicular to the first gate and the second gate.
9. The method of claim 8 , wherein the continuous fin further comprises a third segment and a third gate substantially covering sides and a top of a portion of the third segment, the third segment is parallel to the first segment, arranged at the oblique angle relative to the second segment, and extends from an end of the second segment, and the third gate is substantially parallel to both the first gate and the second gate.
10. The method of claim 8 , wherein the first gate is substantially perpendicular to the first segment of the continuous fin.
11. The method of claim 8 , wherein a width of the continuous fin is sublithographic in dimension.
12. The method of claim 8 , wherein a length of the portion of the second segment covered by the second gate is greater than a length of the portion of the first segment covered by the first gate, the lengths being measured between opposite sides of the first and second gates.
13. The method of claim 8 , further comprising:
forming an array of transistors from the continuous fin and the first and second gates.
14. A method comprising:
patterning a continuous semiconductor fin having a first segment, a second segment, and a third segment, the second segment extends from an end of the first segment to an end of the third segment, the first segment is arranged at an oblique angle relative to the second segment, the third segment is parallel to the first segment and arranged at the oblique angle relative to the second segment, and the first segment, the second segment, and the third segment have a common width along their entire length, wherein a common vertical plane bisects the first segment of the continuous semiconductor fin and a third segment of one of a plurality of continuous semiconductor fins; and
forming a first gate, a second gate, and a third gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous semiconductor fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous semiconductor fin; and the third gate substantially covering sides and a top of a portion of the third segment of the continuous semiconductor fin, wherein the common vertical plane is perpendicular to the first gate, the second gate, and a third gate.
15. The method of claim 14 , wherein the first gate is substantially perpendicular to the first segment of the continuous semiconductor fin.
16. The method of claim 14 , wherein the angle between the first segment and the second segment is greater than 90 degrees.
17. The method of claim 14 , wherein a width of the continuous semiconductor fin is sublithographic in dimension.
18. The method of claim 14 , wherein a length of the portion of the second segment covered by the second gate is greater than a length of the portion of the first segment covered by the first gate, the lengths being measured between opposite sides of the first and second gates.
19. The method of claim 14 , further comprising:
forming an array of transistors from the continuous semiconductor fin and the first and second gates.