Field effect transistor including strained germanium fins
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.
1. A method for fabricating a device, the method comprising:
forming a first mandrel in a p-type field effect transistor region of the device;
forming a second mandrel in an n-type field effect transistor region of the device;
growing a compressive strained germanium fin on a sidewall of the first mandrel;
growing a tensile strained germanium fin on a sidewall of the second mandrel; and
burying one end of the compressive strained germanium fin in a shallow trench isolation layer of the device, such that a bottom and a first side of the one end directly contact the shallow trench isolation layer, and wherein the one end is buried such that a second side of the one end includes a lower portion that directly contacts the first mandrel and an upper portion that directly contacts the shallow trench isolation layer.
2. The method of claim 1 , wherein the p-type field effect transistor region and the n-type field effect transistor region are homo-integrated.
3. The method of claim 1 , wherein the first mandrel and the second mandrel are formed using aspect ratio trapping.
4. The method of claim 1 , wherein the first mandrel contains germanium.
5. The method of claim 4 , wherein the first mandrel has a germanium concentration of between forty and one hundred percent.
6. The method of claim 4 , wherein the first mandrel comprises silicon germanium.
7. The method of claim 6 , wherein the silicon germanium is strain relaxed silicon germanium.
8. The method of claim 1 , wherein the second mandrel comprises at least one Group III-V semiconductor material.
9. The method of claim 8 , wherein the at least one Group III-V semiconductor material is a strain relaxed Group III-V semiconductor material.
10. The method of claim 9 , wherein the at least one Group III-V semiconductor material comprises:
a layer of gallium arsenide; and
a layer of indium gallium arsenide deposited over the layer of gallium arsenide.
11. The method of claim 10 , wherein relative concentrations of indium, gallium, and arsenic in the indium gallium arsenide are chosen so that a lattice structure of the layer of indium gallium arsenide is two percent larger than a lattice structure of a material making up the first mandrel.
12. A method for fabricating a device, the method comprising:
forming a first mandrel in a p-type field effect transistor region of the device;
forming a second mandrel in an n-type field effect transistor region of the device;
growing a compressive strained germanium fin on a sidewall of the first mandrel; and
growing a tensile strained germanium fin on a sidewall of the second mandrel; and
burying one end of the tensile strained germanium fin in a shallow trench isolation layer of the device, such that a bottom and a first side of the one end directly contact the shallow trench isolation layer, and wherein the one end is buried such that a second side of the one end includes a lower portion that directly contacts the strain relaxed Group III-V semiconductor material and an upper portion that directly contacts the shallow trench isolation layer.
13. The method of claim 12 , wherein the first mandrel contains germanium.
14. The method of claim 13 , wherein the first mandrel comprises silicon germanium.
15. The method of claim 12 , wherein the second mandrel comprises at least one strain relaxed Group III-V semiconductor material.
16. The method of claim 12 , wherein the at least one strain relaxed Group III-V semiconductor material comprises:
a layer of gallium arsenide; and
a layer of indium gallium arsenide deposited over the layer of gallium arsenide, wherein relative concentrations of indium, gallium, and arsenic in the indium gallium arsenide are chosen so that a lattice structure of the layer of indium gallium arsenide is two percent larger than a lattice structure of a material making up the first mandrel.
17. The method of claim 12 , wherein the p-type field effect transistor region and the n-type field effect transistor region are homo-integrated.
18. A method for fabricating a device, the method comprising:
forming a first mandrel in a p-type field effect transistor region of the device, wherein the first mandrel comprises strain relaxed silicon germanium;
forming a second mandrel in an n-type field effect transistor region of the device, wherein the second mandrel comprises at least one strain relaxed Group III-V semiconductor material, wherein the at least one strain relaxed Group III-V semiconductor material comprises:
a layer of gallium arsenide; and
a layer of indium gallium arsenide deposited over the layer of gallium arsenide, wherein relative concentrations of indium, gallium, and arsenic in the indium gallium arsenide are chosen so that a lattice structure of the layer of indium gallium arsenide is two percent larger than a lattice structure of the strain relaxed silicon germanium;
growing a compressive strained germanium fin on a sidewall of the first mandrel; and
growing a tensile strained germanium fin on a sidewall of the second mandrel.
19. The method of claim 18 , wherein the p-type field effect transistor region and the n-type field effect transistor region are homo-integrated.
20. The method of claim 18 , wherein the strain relaxed silicon germanium has a germanium concentration of between forty and one hundred percent.