Multilayer dielectric structures for semiconductor nano-devices
View Patent ↗Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
1. A method for fabricating a semiconductor structure, comprising:
forming a BEOL (back end of line) interconnect structure comprising a metal line;
forming a conformal multilayer barrier structure on the metal line, wherein forming the conformal multilayer barrier structure comprises:
forming a first multilayer structure directly on the metal line, wherein the first multilayer structure comprises a plurality of stoichiometric, insulating silicon nitride (SiN) layers, wherein each SiN layer in the first multilayer structure is in direct contact with at least one other SiN layer in the first multilayer structure; and
forming a second multilayer structure directly on the first multilayer structure, wherein the second multilayer structure comprises a plurality of insulating silicon oxynitride (SiNO) layers, wherein the SiNO layers are in-situ oxidized SiN layers with a varying oxygen composition profile, wherein each SiNO layer in the second multilayer structure is in direct contact with at least one other SiNO layer in the second multilayer structure,
wherein each SiN and SiNO layer in the first and second multilayer structures has a thickness of less than or equal to about 2 nanometers.
2. The method of claim 1 , wherein forming the first multilayer structure comprises:
depositing a layer of SiN; and
performing a plasma nitridation process on the layer of SiN to densify and control a stress characteristic of the layer of SiN.
3. The method of claim 2 , further comprising adding one or more reactant species as part of the plasma nitridation process to add Phosphorus (P), Fluorine (F), Boron (B), or Carbon (C) atoms, or a combination thereof, in the layer of SiN.
4. The method of claim 1 , wherein forming the second multilayer structure comprises:
depositing a layer of SiN; and
performing a plasma oxidation process on the layer of SiN to oxidize the layer of SiN and form a SiNO layer.
5. The method of claim 4 , further comprising adding one or more reactant species as part of the plasma oxidation process to add Phosphorus (P), Fluorine (F), Boron (B), or Carbon (C) atoms, or a combination thereof, in the SiNO layer.
6. The method of claim 1 , wherein each of the plurality of SiN and SiON layers of the conformal multilayer barrier structure are formed as conformal layers to provide a step coverage with a conformality of about 70 percent or greater.
7. The method of claim 1 , wherein a total thickness of the conformal multilayer barrier structure is about 25 nanometers or less.
8. The method of claim 1 , wherein forming the conformal multilayer barrier structure further comprises forming a third multilayer structure directly on the second multilayer structure, wherein the third multilayer structure comprises a plurality of stoichiometric, insulating SiN layers.
9. The method of claim 1 , wherein forming the conformal multilayer barrier structure further comprises forming one or more SiN or SiNO layers of each of the first and second multilayer structures to have varying compositions of Phosphorus (P), Fluorine (F), Boron (B), or Carbon (C) atoms, or a combination thereof.
10. The method of claim 1 , wherein the conformal multilayer barrier structure has an effective dielectric constant of less than about 6.5 and greater than about 4.0.
11. The method of claim 1 , wherein the BEOL structure comprises a copper damascene wire formed in an ILD (inter-level dielectric) layer, and wherein the conformal multilayer barrier structure is a capping layer that is disposed on the ILD layer and on an exposed surface of the copper damascene wire.
12. A method for fabricating a semiconductor structure, comprising;
forming a conformal multilayer barrier structure consisting only of a plurality (n) of insulating silicon oxynitride (SiNO) layers, wherein n is an integer that is greater than 3, wherein each insulating SiNO layer is a separately deposited and in-situ oxidized SiN layer with a varying oxygen composition profile, wherein each insulating SiNO layer is formed by depositing a layer of SiN, and performing a plasma oxidation process on the layer of SiN to oxidize the layer of SiN and form the insulating SiNO layer,
wherein each insulating SiNO layer of the conformal multilayer barrier structure has a thickness of less than or equal to about 2 nanometers,
wherein at least one SiNO layer in the conformal multilayer barrier structure is disposed between and in direct contact with at least two other SiNO layers in the conformal multilayer barrier structure, and
wherein the conformal multilayer barrier structure serves as a barrier layer disposed between two layers or elements of the semiconductor structure.
13. The method of claim 12 , wherein a total thickness of the conformal multilayer barrier structure is about 25 nanometers or less.
14. The method of claim 12 , further comprising adding one or more reactant species as part of the plasma oxidation process to add Phosphorus (P), Fluorine (F), Boron (B), or Carbon (C) atoms, or a combination thereof, in the SiNO layer.
15. The method of claim 12 , wherein the conformal multilayer barrier structure provides a step coverage with a conformality of about 70 percent or greater.
16. The method of claim 12 , wherein the semiconductor structure comprises a transistor device, and wherein the conformal multilayer barrier structure is a spacer formed on a sidewall of a gate structure of the transistor device.
17. The method of claim 12 , wherein the semiconductor structure comprises a transistor device, and wherein the conformal multilayer barrier structure is a stress liner layer conformally formed over the transistor device to impart a tensile or compressive stress.
18. The method of claim 12 , wherein the semiconductor structure comprises a trench isolation structure formed in a semiconductor substrate, wherein the conformal multilayer barrier structure is conformally formed to line a sidewall and bottom surface of an etched trench of the trench isolation structure.
19. The method of claim 12 , wherein the semiconductor structure comprises a through-silicon via (TSV) structure formed in a semiconductor substrate, wherein the conformal multilayer barrier structure is a liner of the TSV structure.