Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
View Patent ↗A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions.
1. A method comprising:
obtaining a structure including a semiconductor substrate having a first lattice constant, a first epitaxial layer of III-V semiconductor material having a second lattice constant different from the first lattice constant directly adjoining a top surface of the semiconductor substrate, and a plurality of first trenches extending vertically within the first epitaxial layer of III-V semiconductor material, the first trenches having bottom ends within the first epitaxial layer of III-V semiconductor material and terminating a distance above the top surface of the semiconductor substrate;
filling the first trenches with a dielectric material to form a plurality of dielectric regions within the first epitaxial layer of III-V semiconductor material, each dielectric region having a bottom surface adjoining a top surface of the first epitaxial layer of III-V semiconductor material;
removing a portion of the first epitaxial layer of III-V semiconductor material to form a plurality of vertically oriented second trenches between the dielectric regions, and
epitaxially growing a second layer of III-V semiconductor material directly on the first epitaxial layer of III-V semiconductor material and within the plurality of second trenches.
2. The method of claim 1 , wherein the step of removing the portion of the first epitaxial layer of III-V semiconductor material further includes the steps of etching the first epitaxial layer of III-V semiconductor material and discontinuing the etching step prior to extending below the dielectric regions.
3. The method of claim 2 , wherein the first trenches have the same depth.
4. The method of claim 2 , wherein the step of obtaining the structure further includes epitaxially growing a blanket layer to form the first epitaxial layer of III-V semiconductor material on the top surface of the semiconductor substrate, depositing a hard mask on the first epitaxial layer of III-V semiconductor material, patterning the hard mask, and etching the first epitaxial layer of III-V semiconductor material to form the first trenches.
5. The method of claim 4 , wherein the step of etching the first epitaxial layer of III-V semiconductor material includes using a directional etch process.
6. The method of claim 5 , further including the step of stripping the hard mask subsequent to etching the first epitaxial layer of III-V semiconductor material.
7. The method of claim 6 , wherein the semiconductor substrate is comprised of silicon (100).
8. The method of claim 6 , wherein the second trenches have depths exceeding 50 nm.
9. The method of claim 6 , wherein each of the second trenches has a depth and a width dimension, the depth exceeding the width dimension by at least a factor of three.
10. The method of claim 9 , further including the steps of forming FET devices on the second epitaxial layer of III-V semiconductor material.
11. The method of claim 4 , wherein the step of epitaxially growing the blanket layer further includes growing a first III-V semiconductor material directly on the top surface of the substrate and a second III-V semiconductor material directly on the first III-V semiconductor material.
12. The method of claim 11 , wherein the second III-V semiconductor material has a larger lattice constant than the first III-V semiconductor material, and further wherein the second trenches terminate within the second III-V semiconductor material.
13. The method of claim 1 , wherein each of the second trenches has a depth and a width dimension, the depth exceeding the width dimension by at least a factor of ten.
14. The method of claim 1 , wherein the step of epitaxially growing the blanket layer further includes growing a plurality of III-V semiconductor sub-layers having increasing lattice constants in order of deposition, a first sub-layer directly contacting the substrate, further wherein the second trenches terminate within one of the III-V semiconductor layers above the first sub-layer.
15. The method of claim 14 , wherein the first sub-layer has a lattice mismatch with the substrate and includes misfit defects.
16. The method of claim 15 , further including removing the portion of the first epitaxial layer of III-V material down to a bottom of the dielectric regions.
17. The method of claim 16 , wherein the first sub-layer is a gallium arsenide layer.