Method for forming a semiconductor structure containing high mobility semiconductor channel materials
View Patent ↗A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer.
1. A method of forming a semiconductor structure, said method comprising:
providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer;
forming hard mask material portions having an opening that exposes a portion of said germanium-containing layer on said substrate;
etching through said opening to provide an undercut region in said germanium-containing layer, said undercut region is located between two remaining portions of said germanium-containing layer;
growing a III-V compound semiconductor material within said undercut region and laterally outwards from sidewall surfaces of said two remaining portions of said germanium-containing layer; and
removing portions of said III-V compound semiconductor material to provide III-V compound semiconductor material portions located between said two remaining portions of said germanium-containing layer, wherein said growing comprises an aspect ratio trapping process, and wherein defect-containing regions are formed adjacent each said sidewall surface of said two remaining portions of said germanium-containing layer, and wherein said defect-containing regions are removed by said removing said portions of said III-V compound semiconductor material.
2. The method of claim 1 , wherein said germanium-containing layer is selected from unalloyed germanium, a silicon germanium alloy and a multilayered stacks of germanium and a silicon germanium alloy.
3. The method of claim 1 , wherein said etching comprises a lateral etch, and said lateral etch comprises hydrogen peroxide or gaseous HCl.
4. The method of claim 3 , wherein after said etching, one of said hard mask material portions overhangs one of said two remaining portions of said germanium-containing layer, and another of said hard mask material portions overhangs another of said two remaining portions of said germanium containing layer.
5. The method of claim 1 , wherein said growing further forms an overgrowth region of said III-V compound semiconductor material, and wherein said overgrowth region is also removed by said removing said portions of said III-V compound semiconductor material.
6. The method of claim 1 , wherein said defect-containing regions contain defects that end at the bottommost surface of one of said hard mask material portions and a topmost surface of said insulator layer.
7. The method of claim 1 , wherein said removing said portions of said III-V compound semiconductor material comprises forming trench isolation openings that extend to topmost surface of said insulator layer, and forming a trench dielectric structure within each of said trench isolation openings.
8. The method of claim 7 , wherein said forming said trench dielectric structure comprises filling each trench isolation opening with a trench dielectric material, and removing an upper portion of said trench dielectric material and each of said hard mask material portions.
9. The method of claim 8 , further comprising forming a first functional gate structure on a surface of each of said III-V compound semiconductor material portions and forming a second functional gate structure on a surface of each of said two remaining portions of said germanium-containing layer.
10. The method of claim 8 , wherein prior to forming said first and second functional gate structures, each of said III-V compound semiconductor material portions and each of said two remaining portions of said germanium-containing layer are patterning into fins.
11. The method of claim 1 , wherein said removing said portions of said III-V compound semiconductor material comprises forming trench isolation openings that extend into said handle substrate, and forming a trench dielectric structure within each of said trench isolation openings.
12. The method of claim 11 , wherein said forming said trench dielectric structure comprises filling each trench isolation opening with a trench dielectric material, and removing an upper portion of said trench dielectric material and each of said hard mask material portions.
13. The method of claim 12 , further comprising forming a first functional gate structure on a surface of each of said III-V compound semiconductor material portions and forming a second functional gate structure on a surface of each of said two remaining portions of said germanium-containing layer.
14. The method of claim 13 , wherein prior to forming said first and second functional gate structures, each of said III-V compound semiconductor material portions and each of said two remaining portions of said germanium-containing layer are patterning into fins.