Integrated circuit having strained fins on bulk substrate
View Patent ↗A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins. The third sub-set of fins is composed of a second semiconductor material that differs from the first semiconductor material. Each fin of the third subset has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set. At least one structure formed by the method is also disclosed.
1. A structure, comprising:
a strain relaxed buffer disposed on a surface of a substrate;
a set of fins disposed on a surface of the strain relaxed buffer, the set of fins comprised of a first subset of fins comprised of s-Si 1-x Ge x and a second subset of fins comprised of s-Si, where the strain relaxed buffer is comprised of Si 1-x Ge x , where x has a non-zero value=n, where the first subset of fins are comprised of Si 1-x Ge x where x in the first subset of fins has a value=m, where m>n; and
a layer disposed in a top surface portion of the strain relaxed buffer of Si 1-x Ge x , the layer being disposed at least between individual fins of the set of fins, where x in the layer has the value=m.
2. The structure as in claim 1 , where n is equal to about 0.25, and where m is equal to about 0.50.
3. The structure as in claim 1 , further comprising a counter-doped region at a bottom portion of each individual one of the set of fins to provide electrical isolation.