IP Library Granted Patent US 10,083,850
Granted Patent B2
US 10,083,850 · App. 15/404,362 · Granted Sep 25, 2018

Method of forming a flexible semiconductor layer and devices on a flexible carrier

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Quick Facts
Patent No.
US 10,083,850
App. No.
15/404,362
Granted
Sep 25, 2018
Kind
B2
Abstract

A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate.

Claims (45)

1. A method for fabricating a semiconductor device, comprising:

providing a structure comprising a stressor layer stack on a first surface of a semiconductor substrate;

forming an interfacial release layer on an exposed second surface of the semiconductor substrate;

adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy;

removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate;

processing the semiconductor substrate by isolating cells in the semiconductor substrate by applying a hardmask to the semiconductor substrate and etching exposed semiconductor substrate down to the epoxy; and

removing the hardmask and applying a pressure-sensitive tape to the semiconductor substrate to remove the semiconductor substrate from the interfacial release layer;

wherein processing the semiconductor substrate further comprises one or more of patterning the semiconductor substrate, thermally treating the semiconductor substrate, thinning the semiconductor substrate, and depositing a film on the semiconductor substrate.

2. The method of claim 1 , wherein forming an interfacial release layer on an exposed second surface of the semiconductor substrate comprises thermally evaporating an aluminum-containing compound on the semiconductor substrate.

3. The method of claim 2 , further comprising introducing a contaminant to a surface of the semiconductor substrate prior to thermally evaporating an aluminum-containing compound on the semiconductor substrate.

4. The method of claim 1 , wherein adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy comprises using pressure to substantially uniformly distribute the epoxy on at least a portion of the handle substrate to facilitate a substantially bubble-free bond between the handle substrate and the semiconductor substrate.

5. The method of claim 1 , wherein the semiconductor substrate comprises 100-oriented silicon material.

6. The method of claim 1 , wherein the semiconductor substrate is a material selected from the group consisting of silicon, germanium, SiGe, bulk III-V materials, any of the foregoing materials further including epitaxially grown semiconductor layers, any of the foregoing materials further including doped layers, metallic layers, and/or passivating layers, and combinations of the foregoing materials.

7. The method of claim 1 , wherein the semiconductor substrate comprises a silicon or silicon-containing semiconductor material and the interfacial release layer comprises aluminum.

8. The method of claim 1 , wherein the releasable tape applied to the stressor layer is a UV releasable tape.

9. The method of claim 1 , further comprising separating the semiconductor substrate along a plane extending longitudinally through the semiconductor substrate parallel to the first surface of the semiconductor substrate to reduce a thickness of the semiconductor substrate and expose a second surface of the semiconductor substrate.

10. The method of claim 9 , wherein separating the semiconductor substrate along a plane extending longitudinally through the semiconductor substrate comprises mechanically guiding the at least a portion of the stressor layer stack to induce and sustain a spalling mode fracture.

11. A method for fabricating a semiconductor device, comprising:

providing a structure comprising a stressor layer stack on a first surface of a semiconductor substrate;

forming an interfacial release layer on an exposed second surface of the semiconductor substrate;

adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy;

removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate;

processing the semiconductor substrate by isolating cells in the semiconductor substrate by applying a hardmask to the semiconductor substrate and etching exposed semiconductor substrate down to the epoxy; and

removing the hardmask and applying a pressure-sensitive tape to the semiconductor substrate to remove the semiconductor substrate from the interfacial release layer;

wherein adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy comprises using pressure to substantially uniformly distribute the epoxy on at least a portion of the handle substrate to facilitate a substantially bubble-free bond between the handle substrate and the semiconductor substrate.

12. The method of claim 11 , wherein providing a structure comprising a stressor layer stack comprises forming the stressor layer stack by

depositing an adhesion layer on the semiconductor substrate,

depositing a seed layer on the adhesion layer,

depositing a stressor layer on the seed layer, and

applying a releasable tape to the stressor layer.

13. The method of claim 11 , wherein the semiconductor substrate comprises 100-oriented silicon material.

14. A method for fabricating a semiconductor device, comprising:

providing a structure comprising a stressor layer stack on a first surface of a semiconductor substrate;

forming an interfacial release layer on an exposed second surface of the semiconductor substrate;

adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy;

removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate;

processing the semiconductor substrate by isolating cells in the semiconductor substrate by applying a hardmask to the semiconductor substrate and etching exposed semiconductor substrate down to the epoxy; and

removing the hardmask and applying a pressure-sensitive tape to the semiconductor substrate to remove the semiconductor substrate from the interfacial release layer;

further comprising separating the semiconductor substrate along a plane extending longitudinally through the semiconductor substrate parallel to the first surface of the semiconductor substrate to reduce a thickness of the semiconductor substrate and expose a second surface of the semiconductor substrate.

15. The method of claim 14 , wherein providing a structure comprising a stressor layer stack comprises forming the stressor layer stack by

depositing an adhesion layer on the semiconductor substrate,

depositing a seed layer on the adhesion layer,

depositing a stressor layer on the seed layer, and

applying a releasable tape to the stressor layer.

16. The method of, claim 14 , wherein the semiconductor substrate comprises 100-oriented silicon material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2017
From: BEDELL, STEPHEN W.; SADANA, DEVENDRA K.; SAENGER, KATHERINE L.; SALHI, ABDELMAJID
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040954/0216 →