Selective dopant junction for a group III-V semiconductor device
View Patent ↗An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.
1. A method of forming a dopant junction in a semiconductor device, the method comprising:
performing a surface modification treatment on an exposed surface of a semiconductor layer;
depositing an n-type dopant material for a Group III-V semiconductor material on the exposed surface of the semiconductor layer;
performing a low temperature anneal in an oxygen free environment in order to drive the dopant material into the semiconductor layer;
depositing a metal layer on the dopant material; and
alloying the metal layer with the dopant material to form a semiconductor device junction; wherein:
the semiconductor layer is composed of a Group III-V semiconductor material;
the surface modification treatment occurs in a low pressure vacuum chamber and wherein the surface modification treatment includes applying a low velocity stream of gaseous hydrogen to the exposed surface of the semiconductor layer in order for oxygen desorption to occur to form a water vapor, which thereby removes a plurality of surface oxides from the exposed surface of the semiconductor layer in order to provide an oxide-free surface for material adhesion, and wherein after the surface modification treatment, the semiconductor device remains in the oxygen free environment; and
each of the above processes occur at a low temperature.
2. The method of claim 1 , wherein the low temperature at which each of the processes occur is a temperature less than or equal to 650° Celsius.
3. The method of claim 1 , wherein the surface modification treatment is performed at 10 −4 TORR to 10 −10 TORR.
4. The method of claim 1 , wherein depositing the dopant material is done by a selective epitaxial growth of the dopant material.
5. The method of claim 1 , wherein depositing the n-type dopant material is depositing the n-type dopant material composed of at least one of: Ge, SiGe, GeSn, Sn, SiC, SiGeC, GeC, and InP.
6. The method of claim 1 , wherein the low temperature anneal occurs in a hydrogen plasma.
7. The method of claim 1 , wherein the low temperature anneal forms a region in the semiconductor layer under the dopant material, and wherein the region is composed of the semiconductor material and a portion of the dopant material.
8. The method of claim 1 , wherein alloying the metal layer with the dopant material consumes the dopant layer.
9. The method of claim 1 , wherein after alloying the metal layer with the dopant material, the exposed surface of the semiconductor layer where the dopant material was deposited is oxide free.
10. A semiconductor structure with a dopant junction in a semiconductor device, comprising:
a Group III-V semiconductor layer, wherein a surface modification treatment is performed on an exposed surface of the semiconductor layer in an oxygen free environment, and wherein the surface modification treatment occurs in a low pressure vacuum chamber and includes applying a low velocity stream of gaseous hydrogen to the exposed surface of the semiconductor layer in order for oxygen desorption to occur to form a water vapor, thereby removing a plurality of surface oxides from the exposed surface of the semiconductor layer;
a region in the Group III-V semiconductor layer with an n-type dopant material for a Group III-V semiconductor material forming the dopant junction; and
an alloy layer composed of a metal and the dopant material, wherein the alloy layer is over the region in the Group III-V semiconductor layer with the dopant material.
11. The semiconductor structure of claim 10 , wherein the Group III-V semiconductor layer is at least one of: InGaAs, InP and GaAs.
12. The semiconductor structure of claim 10 , wherein a dopant layer is not present between the alloy layer and the region in the Group III-V semiconductor layer with the n-type dopant material.
13. The semiconductor structure of claim 10 , wherein the n-type dopant material is Si.
14. The semiconductor structure of claim 10 , wherein the n-type dopant material is at least one of: Ge, SiGe, GeSn, Sn, SiC, SiGeC, GeC, and InP.
15. The semiconductor structure of claim 10 , wherein the alloy layer is an alloy of a transitional metal and the n-type dopant material for the Group III-V semiconductor material.
16. The semiconductor structure of claim 10 , wherein the alloy layer is an alloy of Ni and Si.