Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs

1. An integrated circuit with an n-region including n-type FinFETs and a p-region including p-type FinFETs, the integrated circuit formed at least in part by performing the steps of:

forming a silicon-germanium (SiGe) layer consisting essentially of silicon (Si) and germanium (Ge);

recessing the SiGe layer to form a recessed SiGe layer in the n-region while leaving an intact SiGe layer in the p-region;

forming a Si layer consisting essentially of Si on the recessed SiGe layer in the n-region;

patterning the Si layer and the recessed SiGe layer in the n-region to form a Si/SiGe fin comprising a Si fin portion disposed on a recessed SiGe fin portion;

patterning the intact SiGe layer in the p-region to form an intact SiGe fin; and

selectively oxidizing the recessed SiGe fin portion in the n-region utilizing an oxidation process having an oxidation rate in the recessed SiGe fin portion faster than an oxidation rate in the Si fin portion.

2. The integrated circuit of claim 1 , wherein the step of selectively oxidizing the SiGe fin portion increases tensile strain in the Si fin portion.

3. The integrated circuit of claim 1 , wherein the intact SiGe fin in the p-region is compressively strained.

4. An integrated circuit including n-type FinFETs in an n-region and p-type FinFETs in a p-region, the integrated circuit comprising:

an n-type fin in the n-region comprising a silicon (Si) fin portion disposed on an oxidized fin portion, the Si fin portion consisting essentially of Si, and the oxidized fin portion consisting essentially of Si, germanium (Ge) and oxygen; and

a p-type fin in the p-region consisting essentially of Si and Ge.

5. The integrated circuit of claim 4 , wherein the Si fin portion of the n-type fin is tensily strained, and the p-type fin is compressively strained.

6. The integrated circuit of claim 4 , further comprising a buried oxide layer underlying the n-type fin and the p-type fin.