III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology
In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.
1. A method of co-fabricating at least one CMOS FET device and at least one bipolar transistor device on a wafer, the method comprising the steps of:
forming at least one CMOS FET dummy gate and at least one bipolar transistor dummy gate on the wafer, wherein the CMOS FET dummy gate is present over a portion of the wafer that serves as a channel region of the CMOS FET device and the bipolar transistor dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor;
doping the wafer to form emitter and collector regions on both sides of the bipolar transistor dummy gate;
doping the wafer to form source and drain regions on both sides of the CMOS FET dummy gate;
depositing a dielectric filler layer onto the wafer surrounding the CMOS FET dummy gate and the bipolar transistor dummy gate;
removing the CMOS FET dummy gate and the bipolar transistor dummy gate selective to the dielectric filler layer, wherein removal of the CMOS FET dummy gate results in at least one first trench being formed in the dielectric filler layer and removal of the bipolar transistor dummy gate results in at least one second trench being formed in the dielectric filler layer;
recessing the base of the bipolar transistor;
re-growing the base of the bipolar transistor from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material;
forming a replacement gate of the CMOS FET device in the first trench over the channel region of the CMOS FET device; and
forming contacts to the replacement gate of the CMOS FET device and to the base of the bipolar transistor device.
2. The method of claim 1 , further comprising the step of:
forming spacers on opposite sides of the CMOS FET dummy gate and on opposite sides of the bipolar transistor dummy gate.
3. The method of claim 2 , further comprising the step of
forming inner spacers in the bipolar transistor device.
4. The method of claim 1 , wherein the base of the bipolar transistor is re-grown from a III-V epitaxial material selected from the group consisting of aluminum gallium arsenide, aluminum gallium nitride, aluminum indium arsenide, aluminum nitride, gallium antimonide, gallium arsenide, gallium nitride, indium antimonide, indium arsenide, indium gallium arsenide, indium gallium nitride, indium nitride, indium phosphide and combinations comprising at least one of the foregoing materials.
5. The method of claim 1 , further comprising the step of:
doping the base of the bipolar transistor, in situ, during re-growth of the base from the epitaxial material.
6. The method of claim 1 , further comprising the step of:
doping the base of the bipolar transistor using solid source diffusion.
7. The method of claim 1 , wherein the step of forming contacts to the replacement gate of the CMOS FET device and to the base of the bipolar transistor device comprises the steps of
depositing a polysilicon layer onto the wafer covering the CMOS FET device and the bipolar transistor device;
patterning the polysilicon layer such that the polysilicon layer remains only on the replacement gate of the CMOS FET device and on the base of the bipolar transistor;
depositing a metal onto the wafer;
reacting the metal with the patterned polysilicon layer to form the contacts to the replacement gate of the CMOS FET device and to the base of the bipolar transistor device; and
removing any unreacted metal.
8. The method of claim 1 , further comprising the step of:
forming contacts to the source and drain regions of the CMOS FET device and to the emitter and collector regions of the bipolar transistor device.
9. The method of claim 8 , further comprising the steps of:
removing the dielectric filler layer;
depositing a metal onto the wafer;
reacting the metal with the source and drain regions to form the contacts to the source and drain regions of the CMOS FET device and reacting the metal with the emitter and collector regions to form the contacts to the emitter and collector regions of the bipolar transistor device.
10. The method of claim 9 , further comprising the step of:
thickening the base of the bipolar transistor device using epitaxy.