Strain relaxed buffer layers with virtually defect free regions
View Patent ↗A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions. An anneal is then performed on the strain relaxed buffer layer to propagate and amass the misfit dislocation defects and threading dislocation defects at a sidewall of each of the non-recessed regions of the first semiconductor material.
1. A method of forming a semiconductor structure, said method comprising:
providing a first semiconductor material of a first lattice constant, said first semiconductor material having a surface containing at least one recessed region and non-recessed regions adjoining said at least one recessed region;
forming a second semiconductor material of a second lattice constant that is different from said first lattice constant on said surface of said first semiconductor material, wherein said second semiconductor material is strained;
converting said second semiconductor material that is strained into a strain relaxed buffer layer, said strain relaxed buffer layer containing misfit dislocation defects and threading dislocation defects; and
annealing said strain relaxed buffer layer to propagate and amass said misfit dislocation defects and threading dislocation defects at a sidewall of each of said non-recessed regions of said first semiconductor material, wherein said annealing forms a first region located in said strain relaxed buffer layer that is located directly above said at least one recessed region of said first semiconductor material, while forming second regions that are located directly above each non-recessed region of said first semiconductor material, wherein each first region has a first threading dislocation defect density and each second region has a second threading dislocation defect density that is greater than said first threading dislocation defect density.
2. The method of claim 1 , wherein said providing said first semiconductor material comprises a patterning process.
3. The method of claim 1 , wherein said forming said second semiconductor material comprises an epitaxial growth process.
4. The method of claim 1 , wherein said converting said second semiconductor material into said strain relaxed buffer layer comprises:
forming a plurality of ion-induced defects proximate an interface formed between said first and second semiconductor materials; and
performing a strain relaxation anneal.
5. The method of claim 4 , wherein said forming said plurality of ion-induced defects comprises ion implantation.
6. The method of claim 4 , wherein said plurality of ion-induced defects are in the form of bubbles.
7. The method of claim 4 , wherein said stain relaxation anneal comprises heating in an inert ambient at a temperature from 800° C. to 1050° C.
8. The method of claim 4 , wherein said annealing is an extension of said strain relaxation anneal.
9. The method of claim 1 , wherein said second lattice constant of said second semiconductor material is greater than said first lattice constant of said first semiconductor material.
10. The method of claim 9 , wherein said second semiconductor material is a silicon germanium alloy and said first semiconductor material is silicon.
11. The method of claim 1 , wherein said annealing is performed in an inert ambient at a temperature from 800° C. to 1050° C.
12. The method of claim 1 , wherein said first threading dislocation defect density is less than 100/cm 2 , and said second threading dislocation defect density is greater than 1×10 6 /cm 2 .