IP Library Granted Patent US 9,892,925
Granted Patent B2
US 9,892,925 · App. 15/267,357 · Granted Feb 13, 2018

Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy

Inventors: Kangguo Cheng (Schenectady, NY); Pouya Hashemi (White Plains, NY); Shogo Mochizuki (Clifton Park, NY); Alexander Reznicek (Troy, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L21/28132H01L21/28035H01L21/32139H01L29/42364H01L29/42376H01L29/4916H01L29/6656H01L29/66545
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Quick Facts
Patent No.
US 9,892,925
App. No.
15/267,357
Granted
Feb 13, 2018
Kind
B2
Abstract

A method of making a semiconductor device includes forming a gate covered by a hard mask over a substrate; disposing a mask over the gate and the hard mask; patterning the mask to expose a portion of the gate and the hard mask; cutting the gate and hard mask to form two shorter gates, each of the two shorter gates having an exposed end portion; undercutting the exposed end portion of at least one of the two shorter gates to form an overhanging hard mask portion over the exposed end portion; and forming spacers along a gate sidewall and beneath the overhanging hard mask portion.

Claims (15)

1. A method of making a semiconductor device, the method comprising:

cutting a gate having a hard mask disposed thereon to form two shorter gates; and

undercutting an exposed end portion of one of the two shorter gates to form an overhanging hard mask portion over the exposed end portion of one of the two shorter gates;

wherein the gate comprises a polysilicon material or an amorphous silicon material that extends continuously from a substrate beneath the gate to the hard mask.

2. The method of claim 1 , further comprising forming spacers along a gate sidewall and beneath the overhanging hard mask portion.

3. The method of claim 2 , wherein forming spacers comprises depositing a spacer material over the hard mask to fill regions along the gate sidewall and beneath the overhanging hard mask portion.

4. The method of claim 3 , further comprising etching the spacer material by an anisotropic etching process.

5. The method of claim 2 , wherein the spacers have a thickness in a range from about 3 to about 30 nanometers (nm).

6. The method of claim 1 , wherein the overhanging hard mask portion has a width in a range from about 3 to about 30 nm.

7. The method of claim 1 , wherein the exposed end portion has a width in a range from about 40 to about 2,000 nm after undercutting.

8. A method of making a semiconductor device, the method comprising:

cutting a single gate having a hard mask disposed thereon to form two shorter gates from the single gate, each of the two shorter gates having a side portion and an exposed end portion, the side portion having a length dimension that is larger than a width dimension of the exposed end portion; and

undercutting the exposed end portion of one of the two shorter gates to form an overhanging hard mask portion over the exposed end portion of one of the two shorter gates;

wherein the gate comprises a polysilicon material or an amorphous silicon material that extends continuously from a substrate beneath the gate to the hard mask.

9. The method of claim 8 , wherein undercutting the exposed end portion reduces the length dimension.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2016
From: CHENG, KANGGUO; HASHEMI, POUYA; MOCHIZUKI, SHOGO; REZNICEK, ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039763/0956 →
Continuity (3)
Continuation 14964909 · Dec 10, 2015
Continuation 14829856 · Aug 19, 2015
Related Publication 20170053805A1 · Feb 23, 2017