Forming multi-stack nanowires using a common release material

1. A method comprising:

forming a common release layer on a substrate, the common release layer comprising a common release material;

forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers comprising a first material separated by at least one layer comprising the common release material;

forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers comprising a second material separated by at least one layer comprising the common release material;

patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins; and

forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process;

wherein the first material is different than the second material; and

wherein the common release material is different than the first material and the second material.

2. The method of claim 1 , wherein the common release material is gallium phosphide, the first material is silicon germanium and the second material is silicon.

3. The method of claim 1 , wherein patterning each of the first multi-layer stack and the second multi-layer stack comprises utilizing a hard mask formed over portions of the first multi-layer stack and the second multi-layer stack.

4. The method of claim 3 , further comprising:

depositing an anchor layer at ends of each of the one or more fins; and

removing the common release material on the substrate, in the first multi-layer stack and in the second multi-layer stack.

5. The method of claim 4 , further comprising depositing an oxide in one or more spaces formed by removal of the common release material.

6. The method of claim 5 , further comprising:

removing the hard mask formed over portions of the first and second multi-layer stack; and

forming a plurality of dummy gates on portions of the two or more multi-stack nanowires.

7. The method of claim 6 , further comprising forming thin spacers on sides of each of the plurality of dummy gates.

8. The method of claim 7 , further comprising:

selectively removing a first portion of the oxide in regions between the two or more multi-stack nanowires not covered by the plurality of dummy gates and in regions between the two or more multi-stack nanowires and the substrate not covered by the plurality of dummy gates; and

depositing a thin spacer to fill in one or more spaces left by removal of the first portion of the oxide.

9. The method of claim 8 , further comprising forming source/drain regions by doping portions of the two or more multi-stack nanowires not covered by the plurality of dummy gates.

10. The method of claim 9 , further comprising:

forming an insulator in spaces between the plurality of dummy gates and above the source/drain regions;

planarizing the top surface of the insulator; and

removing the plurality of dummy gates.

11. The method of claim 10 , further comprising removing a second portion of the oxide in regions between the two or more multi-stack nanowires not covered by the insulator.

12. The method of claim 11 , further comprising forming a gate stack by depositing a gate material to fill in spaces surrounding the two or more multi-stack nanowires, wherein the gate stack is completely wrapped around the two or more multi-stack nanowires.

13. The method of claim 12 , further comprising depositing a gate cap onto the gate stack.

14. The method of claim 1 , wherein the two or more layers of the first material in the first multi-layer stack form nanowires for a negative-channel field-effect transistor and the two or more layers of the second material in the second multi-layer stack form nanowires for a positive-channel field-effect transistor.

15. The method of claim 1 , wherein the common etch process utilizes a wet etch selective to the first material and the second material.

16. The method of claim 15 , wherein the wet etch comprises a composition of hydrochloric acid, acetic acid and hydrogen peroxide.

17. The method of claim 1 , wherein the first material comprises a first group II-IV material, the second material comprises a second group II-IV material, the common release material comprises a group III-V material, and wherein the common etch process utilizes a given etchant that removes the group III-V material selective to the first group II-IV material and the second group II-IV material.

18. The method of claim 4 , wherein the anchor layer comprises an insulator.

19. The method of claim 13 , wherein the gate material comprises a high-k gate material and the gate cap comprises a dielectric.