IP Library Granted Patent US 9,190,328
Granted Patent B2
US 9,190,328 · App. 14/168,382 · Granted Nov 17, 2015

Formation of fins having different heights in fin field effect transistors

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Quick Facts
Patent No.
US 9,190,328
App. No.
14/168,382
Granted
Nov 17, 2015
Kind
B2
Abstract

A method includes forming at least two fins of a fin field effect transistor (finFET) on a substrate and forming an insulator layer on the at least two fins. A portion of the insulator layer at a top of a first fin of the at least two fins is removed and a sacrificial layer is formed in a top end of the first fin. The method includes etching the sacrificial layer to remove the sacrificial layer to form the first fin having a different fin height than a second fin of the at least two fins.

Claims (38)

1. A method, comprising:

forming at least two fins of a fin field effect transistor (finFET) on a substrate;

forming an insulator layer on the at least two fins;

removing a portion of the insulator layer at a top of a first fin of the at least two fins;

forming a sacrificial layer in a top end of the first fin;

etching the sacrificial layer to remove the sacrificial layer to form the first fin having a different fin height than a second fin of the at least two fins;

wherein forming the sacrificial layer comprises:

depositing silicon germanium (SiGe) on the top of the first fin; and

annealing the SiGe to form the sacrificial layer of SiGe in the first fin.

2. A method, comprising:

forming at least two fins of a fin field effect transistor (finFET) on a substrate;

forming an insulator layer on the at least two fins;

removing a portion of the insulator layer at a top of a first fin of the at least two fins;

forming a sacrificial layer in a top end of the first fin;

etching the sacrificial layer to remove the sacrificial layer to form the first fin having a different fin height than a second fin of the at least two fins;

wherein forming the sacrificial layer includes oxidizing the top of the first fin to form a silicon oxide (SiO) sacrificial layer in the first fin.

3. The method of claim 1 , wherein the at least two fins includes the first fin that is part of a p-type field effect transistor (pFET) and a second fin that is part of an n-type field effect transistor (nFET), and

removing the portion of the insulator on the top of the first fin includes masking the second fin and applying an etch material to the first and second fins to etch the top of the first fin.

4. The method of claim 1 , wherein etching the sacrificial layer includes applying an etching material to the sacrificial layer.

5. The method of claim 4 , wherein the etching material is hydrochloric acid (HCl).

6. The method of claim 1 , further comprising:

forming at least two gate structures on the at least two fins, respectively; and

forming at least two contacts on opposite ends of the at least two fins on opposite sides of the at least two gate structures.

7. An article, comprising:

a first fin of a first fin field-effect transistor (finFET) formed on a substrate;

a second fin of a second finFET formed on the substrate;

an insulator layer formed on the first fin, the second fin, and the substrate, the insulator layer exposing a top portion of the first fin and covering a top portion of the second fin; and

a sacrificial layer formed in the top portion of the first fin, the sacrificial layer configured to be removable by etching, such that a height of the first fin up to the bottom of the sacrificial layer is less than a height of the second fin;

wherein the first finFET is a p-type field-effect transistor (pFET) and the second finFET is an n-type field-effect transistor (nFET).

8. The article of claim 7 , wherein the pFET and the nFET are part of a same static random access memory (SRAM) cell.

9. The article of claim 7 , wherein the sacrificial layer is made of a layer of silicon germanium (SiGe) on a top surface of the first fin and annealed with first fin to form the sacrificial layer in the top portion of the first fin.

10. An article, comprising:

a first fin of a first fin field-effect transistor (finFET) formed on a substrate;

a second fin of a second finFET formed on the substrate;

an insulator layer formed on the first fin, the second fin, and the substrate, the insulator layer exposing a top portion of the first fin and covering a top portion of the second fin; and

a sacrificial layer formed in the top portion of the first fin, the sacrificial layer configured to be removable by etching, such that a height of the first fin up to the bottom of the sacrificial layer is less than a height of the second fin;

wherein the sacrificial layer is made of a silicon oxide (SiO) in the top portion of the first fin.

11. The article of claim 7 , wherein the sacrificial layer is made of a material that is removable by hydrochloric acid (HCl).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2014
From: BASKER, VEERARAGHAVAN S.; YAMASHITA, TENKO; YEH, CHUN-CHEN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 032093/0305 →