Hybrid ETSOI structure to minimize noise coupling from TSV
View Patent ↗In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.
1. A method for forming an electronic device, comprising the steps of:
patterning an extremely thin silicon-on-insulator (ETSOI) layer of an ETSOI wafer into ETSOI segments comprising first ETSOI segments and at least one second ETSOI segment, each of the first ETSOI segments having a width of from about 3 nm to about 20 nm;
forming a gate electrode over a portion of the first ETSOI segments which serves as a channel region of a first transistor, wherein portions of the first ETSOI segments extending out from under the gate electrode serve as source and drain regions of the first transistor;
forming at least one through silicon via (TSV) in the ETSOI wafer adjacent to the first transistor,
wherein the first ETSOI segments are rectangular in shape with first sides having a first length and second sides having a second length, wherein the first length is greater than the second length, wherein the ETSOI segments are oriented with the first sides facing one another and the second sides facing the at least one TSV, and wherein a distance between the at least one TSV and the first transistor on the ETSOI wafer is less than or equal to about 80 μm; and
forming at least one second transistor on the ETSOI wafer comprising the at least one second ETSOI segment having a width that is greater than the width of the first ETSOI segments in the first transistor, wherein a distance between the at least one TSV and the second transistor on the ETSOI wafer is greater than about 80 μm, and wherein the first transistor and the second transistor comprise a hybrid device structure.
2. The method of claim 1 , wherein the ETSOI layer has a thickness of from about 3 nm to about 80 nm.
3. The method of claim 1 , wherein the ETSOI layer has a thickness of from about 3 nm to about 20 nm.
4. The method of claim 1 , wherein the ETSOI layer is patterned using reactive ion etching.
5. The method of claim 1 , wherein the ETSOI layer is patterned into multiple ETSOI segments.
6. The method of claim 5 , wherein a spacing between adjacent first ETSOI segments is from about 3 nm to about 40 nm.
7. The method of claim 1 , wherein the gate electrode comprises at least one metal.
8. The method of claim 1 , wherein the gate electrode comprises doped polysilicon.
9. The method of claim 1 , wherein the step of forming the at least one TSV in the wafer comprises the steps of:
etching a hole in the ETSOI wafer;
depositing an insulation layer into and lining the hole; and
filling the hole with at least one metal to form the at least one TSV in the ETSOI wafer.
10. The method of claim 1 , wherein a distance between the at least one TSV and the first transistor on the ETSOI wafer is less than or equal to about 50 μm.
11. The method of claim 9 , wherein the first transistor is formed on a buried oxide (BOX) of the ETSOI wafer over a substrate of the ETSOI wafer, wherein the at least one TSV extends through the BOX and the substrate, and wherein the insulation layer separates the at least one metal from the BOX and the substrate.