Multiple step anneal method and semiconductor formed by multiple step anneal
View Patent ↗A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.
1. A method of annealing a semiconductor device including a dielectric layer having a lower bulk region and an upper interface region formed on the lower bulk region, the method comprising:
providing the semiconductor device;
heating the semiconductor device to a first temperature for a first period of time sufficient to remove substantially an entirety of physically-adsorbed water from the semiconductor device; and
after the heating of the semiconductor device to the first temperature, heating the semiconductor device to a second temperature, the second temperature being greater than the first temperature, for a second period of time which is less than the first period of time and sufficient to remove chemically-adsorbed water from the semiconductor device, such that a density of the upper interface region is greater than a density of the lower bulk region, and an amount of silicon and oxygen in a composition of the upper interface region is greater than an amount of silicon and oxygen in a composition of the lower bulk region,
wherein the first temperature comprises a temperature between 100° C. and 200° C. and the first period of time comprises a period of approximately 12 hours to 48 hours, and
wherein the second temperature comprises a temperature in a range from 350° C. to 400° C. and the second period of time comprises a period of approximately 0.5 hours to 2 hours.
2. A method according to claim 1 , wherein the first temperature is lower than a temperature required to remove the chemically-adsorbed water from the semiconductor device.
3. A method according to claim 1 , wherein the second temperature is a temperature sufficient to remove the chemically-adsorbed water from the semiconductor device.
4. A method for testing a semiconductor device, the method comprising:
annealing the semiconductor device according to claim 1 ; and
performing a time dependent dielectric breakdown (TDDB) test on the semiconductor device.
5. A method according to claim 1 , wherein the second temperature is a temperature equal to or greater than a temperature at which SiOH breaks down into H 2 O+Si—O—Si.
6. A method according to claim 1 , wherein the semiconductor device, prior to the heating the semiconductor device to the first temperature, comprises adsorbed water.
7. A method according to claim 1 , wherein the semiconductor device includes:
a plurality of metal conductors; and
a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface region and a lower bulk region, the upper interface region having a density greater than a density of the lower bulk region, and
wherein, prior to heating the semiconductor device to the first temperature, the dielectric includes an upper interface region includes including SiOH.
8. A method according to claim 1 , wherein the semiconductor device, prior to the heating the semiconductor device to the first temperature, comprises SiOH.
9. A method according to claim 1 , wherein the semiconductor device, after to the heating the semiconductor device to the second temperature, comprises SiO 2 .
10. A method of annealing a semiconductor device including a dielectric layer having a lower bulk region and an upper interface region formed on the lower bulk region, the method comprising:
providing the semiconductor device;
exposing the semiconductor device to an atmosphere comprising N 2 at a first temperature greater than 100° C. and less than 200° C. for approximately 12 to 48 hours; and
after the exposing of the semiconductor device to an atmosphere comprising N 2 at the first temperature, exposing the semiconductor device to an atmosphere comprising N 2 at a second temperature in a range of 350° C. to 400° C. for approximately 0.5 to 2 hours, such that a density of the upper interface region is greater than a density of the lower bulk region, and an amount of silicon and oxygen in a composition of the upper interface region is greater than an amount of silicon and oxygen in a composition of the lower bulk region.
11. A method according to claim 10 , wherein the semiconductor device comprises a back end of line (BEOL) interconnect wiring structure.
12. A semiconductor device, comprising:
a plurality of metal conductors; and
a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface region and a lower bulk region, the upper interface region having a density 47% to 57% greater than a density of the lower bulk region, and an amount of silicon and oxygen in a composition of the upper interface region being greater than an amount of silicon and oxygen in a composition of the lower bulk region.
13. The semiconductor device of claim 12 , wherein the upper interface region and the lower bulk region of the dielectric comprise Si a C b O c H d , and
wherein a, b, c and d represent a composition of the dielectric, and a and c are greater in the composition of the upper interface region and lesser in the lower bulk region.
14. The semiconductor device of claim 13 , wherein the dielectric comprises a material such that a, b, c and d are smoothly changing between the upper interface region and the lower bulk region.
15. The semiconductor device of claim 13 , wherein the lower bulk region of the dielectric comprises a composition Si a C b O c H d , and
wherein the upper interface region includes N and comprises a composition of Si a C b O c H d N e .
16. The semiconductor device of claim 12 , wherein the semiconductor device comprises a back end of line (BEOL) interconnect wiring structure.
17. The semiconductor device of claim 12 , wherein the dielectric comprises an inner-layer dielectric (ILD).
18. The semiconductor device of claim 12 , further comprising a capping layer disposed on the dielectric.
19. The semiconductor device of claim 12 , wherein the upper interface region comprises SiO 2 .
20. The semiconductor device of claim 12 , wherein the upper interface region is disposed adjacent to the plurality of metal conductors.
21. The method according to claim 1 , wherein the first temperature comprises a temperature between 100° C. and 200° C. and the first period of time comprises a period of approximately 12 hours to 48 hours,
wherein the second temperature comprises a temperature in a range from 350° C. to 400° C. and the second period of time comprises a period of approximately 0.5 hours to 2 hours,
wherein the density of the upper interface region is 47% to 57% greater than a density of the lower bulk region, and
wherein after the heating of the semiconductor device to the second temperature, the composition of the lower bulk region comprises Si a C b O c H d , and the composition of the upper interface region comprises Si a C b O c H d N e .