Methods for contact formation for 10 nanometers and beyond with minimal mask counts
View Patent ↗A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around first, second, and third gates; removing a portion of the hard mask to form an opening that exposes the first, second, and third gates; forming a patterned soft mask on the first, second, and third gates within the opening, a first portion of the patterned soft mask being disposed on the first and second gates, and a second portion of the patterned soft mask being disposed on the second and third gates; removing portions of the dielectric layer to transfer the pattern of the patterned soft mask into the dielectric layer and form first and second contact openings between the first and second gates, and third and fourth contact openings between the second and third gates; and disposing a conductive material in the contact openings.
1. A method of making a semiconductor device, the method comprising:
depositing a hard mask on a dielectric layer disposed on a substrate, the dielectric layer being disposed around a first gate, a second gate, and a third gate extending from an exposed surface of the dielectric layer to the substrate;
removing a portion of the hard mask to form an opening within the hard mask that exposes the first gate, the second gate, and the third gate;
forming a patterned soft mask on the first, second, and third gates within the opening of the hard mask, a first portion of the patterned soft mask being disposed on the first gate and the second gate, and a second portion of the patterned soft mask being disposed on the second gate and the third gate;
removing portions of the dielectric layer to transfer the pattern of the patterned soft mask into the dielectric layer and form a first contact opening and a second contact opening between the first gate and the second gate, and a third contact opening and a fourth contact opening between the second gate and the third gate; and
disposing a conductive material in the first, second, third, and fourth contact openings.
2. The method of claim 1 , wherein the first gate, the second gate, and the third gate comprise hard mask caps, and the hard mask caps are exposed after removing the portion of the hard mask.
3. The method of claim 2 , wherein the hard mask caps comprise silicon nitride.
4. The method of claim 1 , wherein the hard mask comprises amorphous silicon, titanium nitride, or a combination thereof.
5. The method of claim 1 , wherein the patterned soft mask comprises a photoresist material, a polymeric material, or a combination thereof.
6. The method of claim 1 , wherein the first and second contact openings extend from a sidewall of the first gate to a sidewall of the second gate and have a sidewall that is substantially perpendicular to the first gate and the second gate, and the third and fourth contact openings extend from a sidewall of the second gate to a sidewall of the third gate and have a sidewall that is substantially perpendicular to the second gate and third gate.
7. A method of making a semiconductor device, the method comprising:
depositing a hard mask on a dielectric layer disposed on a substrate, the dielectric layer being disposed around a first gate, a second gate, and a third gate extending from an exposed surface of the dielectric layer to the substrate;
removing a portion of the hard mask to form an opening within the hard mask that exposes the first gate, the second gate, and the third gate;
disposing a soft mask material on the first, second, and third gates within the opening of the hard mask;
removing portions of the soft mask material to form a first soft mask portion that is disposed on and extends from the first gate to the second gate, and a second soft mask portion that is disposed on and extends from the second gate to the third gate;
removing portions of the dielectric layer to transfer a pattern of the first soft mask portion into the dielectric layer and form a first contact opening and a second contact opening between the first gate and the second gate, and to transfer a pattern of the second soft mask portion into the dielectric layer and form a third contact opening and a fourth contact opening between the second gate and the third gate; and
disposing a conductive material in the first, second, third, and fourth contact openings.
8. The method of claim 7 , wherein the soft mask material is thicker than the hard mask and extends over the hard mask.
9. The method of claim 7 , wherein the second contact opening is smaller than the first contact opening, and the fourth contact opening is smaller than the third contact opening.
10. The method of claim 7 , wherein the first and second contact openings extend from a sidewall of the first gate to a sidewall of the second gate and have a sidewall that is substantially perpendicular to the first gate and the second gate, and the third and fourth contact openings extends from a sidewall of the second gate to a sidewall of the third gate and have a sidewall that is substantially perpendicular to the second gate and third gate.
11. The method of claim 7 , wherein the soft mask material is an organic material.
12. The method of claim 7 , wherein a hard mask material is amorphous silicon, titanium nitride, or a combination thereof.
13. The method of claim 7 , wherein the conductive material is tungsten, aluminum copper, or any combination thereof.
14. The method of claim 7 , further comprising removing the hard mask, the first soft mask portion, and the second soft mask portion before disposing the conductive material in the first, second, third, and fourth contact openings.
15. The method of claim 7 , wherein the first gate, the second gate, and the third gate comprise hard mask caps, and the hard mask caps are exposed after removing the portion of the hard mask.