Porous silicon relaxation medium for dislocation free CMOS devices
View Patent ↗A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
1. A complementary metal oxide semiconductor device, comprising:
a silicon on insulator substrate;
first fins formed in a first region from a tensile-strained silicon layer on a buried dielectric layer of the substrate;
a converted dielectric layer formed on the buried dielectric layer of the substrate in a second region; and
second fins formed in the second region in a compression-strained layer on the converted dielectric layer;
wherein the first and second fins include different heights and the first fins are included in N-type field effect transistors and the second fins are included in P-type field effect transistors.
2. The device as recited in claim 1 , wherein the second fins include SiGe.
3. The device as recited in claim 1 , wherein the different heights of the N-type field effect transistors and the P-type field effect transistors provide an N/P ratio.
4. The device as recited in claim 1 , wherein the converted dielectric layer include a silicon oxide layer converted from porous silicon.
5. A complementary metal oxide semiconductor device, comprising:
a strained silicon on insulator substrate;
boron doped fins formed in a first region from a tensile-strained silicon layer on a buried dielectric layer of the substrate;
a silicon oxide layer formed on the buried dielectric layer of the substrate in a second region; and
SiGe fins formed in the second region in a compression-strained layer on the converted dielectric layer;
wherein the boron doped and SiGe fins include different heights and the boron doped fins are included in N-type field effect transistors and the SiGe fins are included in P-type field effect transistors.