Fabrication of III-V-on-insulator platforms for semiconductor devices
View Patent ↗Embodiments of the present invention provide III-V-on-insulator (IIIVOI) platforms for semiconductor devices and methods for fabricating the same. According to one embodiment, compositionally-graded buffer layers of III-V alloy are grown on a silicon substrate, and a smart cut technique is used to cut and transfer one or more layers of III-V alloy to a silicon wafer having an insulator layer such as an oxide. One or more transferred layers of III-V alloy can be etched away to expose a desired transferred layer of III-V alloy, upon which a semi-insulating buffer layer and channel layer can be grown to yield IIIVOI platform on which semiconductor devices (e.g., planar and/or 3-dimensional FETs) can be fabricated.
1. A method for fabricating a III-V-on-insulator (IIIVOI) platform for a semiconductor device, comprising:
growing a plurality of compositionally-graded III-V buffer layers on a first substrate;
implanting ions into one or more of the plurality of compositionally-graded III-V buffer layers to create a cleave plane;
bonding a second substrate to one or more of the plurality of compositionally-graded III-V buffer layers;
separating, along the cleave plane, the second substrate and the one or more compositionally-graded III-V buffer layers bonded to the second substrate from the first substrate and one or more compositionally-graded III-V buffer layers bonded to the first substrate;
growing a semi-insulating buffer layer on one of the one or more compositionally-graded III-V buffer layers bonded to the second substrate; and
growing a channel layer on the semi-insulating buffer layer.
2. The method of claim 1 , wherein the first substrate comprises silicon.
3. The method of claim 1 , wherein the second substrate comprises a silicon wafer having an oxide layer.
4. The method of claim 1 , further comprising:
selectively removing one or more compositionally-graded III-V buffer layers to expose a desired compositionally-graded III-V buffer layer on which to grow the semi-insulating buffer layer.
5. The method of claim 4 , wherein the semi-insulating buffer layer is grown on the desired compositionally-graded III-V buffer layer.
6. The method of claim 1 , wherein the plurality of compositionally-graded III-V buffer layers comprise a plurality of III-V alloy layers having bond lengths that increase from a first compositionally-graded III-V buffer layer disposed closest to the first substrate to a second compositionally-graded III-V buffer layer disposed furthest from the first substrate.
7. The method of claim 6 , wherein the plurality of compositionally-graded III-V buffer layers comprise indium gallium arsenide (InGaAs) alloys that increase in concentration of gallium (Ga) and decrease in concentration of indium (In) from the first compositionally-graded III-V buffer layer to the second compositionally-graded III-V buffer layer.
8. The method of claim 6 , wherein the composition of the second compositionally-graded III-V buffer layer is selected to have a band energy gap that is less than that of the semi-insulating buffer layer.
9. The method of claim 6 , wherein the semi-insulating buffer layer is grown on the second compositionally-graded III-V buffer layer.