IP Library Granted Patent US 9,847,259
Granted Patent B2
US 9,847,259 · App. 14/743,561 · Granted Dec 19, 2017

Germanium dual-fin field effect transistor

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Quick Facts
Patent No.
US 9,847,259
App. No.
14/743,561
Granted
Dec 19, 2017
Kind
B2
Abstract

In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.

Claims (18)

1. A method for fabricating a field effect transistor, the method comprising:

providing a pair of fins positioned in a spaced apart relation, each of the fins in the pair of fins formed from a first material comprising germanium;

providing source and drain regions formed on opposite ends of the pair of fins, wherein the source and drain regions are formed from a second material, different from the first material, comprising silicon; and

providing a gate wrapped around the pair of fins, between the source and drain regions.

2. The method of claim 1 , wherein the source and drain regions are formed of doped silicon.

3. The method of claim 2 , further comprising:

providing an extension positioned beneath the source and drain regions, wherein the extension is formed of doped silicon.

4. The method of claim 3 , wherein the extension is N+ doped, and the doped silicon of the source and drain regions is N++ doped.

5. The method of claim 4 , wherein a doping concentration of the extension is between approximately 5e18 and 5e19 electrons per cubic centimeter, and a doping concentration of the source and drain regions is above approximately 1e20 electrons per cubic centimeter.

6. The method of claim 3 , wherein the extension is P+ doped, and the doped silicon of the source and drain regions is P++ doped.

7. The method of claim 1 , wherein the field effect transistor is an N-type field effect transistor.

8. The method of claim 1 , wherein the germanium is epitaxially grown over silicon.

9. A method for fabricating a field effect transistor, the method comprising:

providing a pair of fins positioned in a spaced apart relation, each of the fins in the pair of fins formed from a first semiconductor material;

providing source and drain regions formed on opposite ends of the pair of fins, wherein the source and drain regions are formed from a second semiconductor material different from the first semiconductor material; and

providing a gate wrapped around the pair of fins, between the source and drain regions.

10. The method of claim 9 , wherein the first semiconductor material is germanium.

11. The method of claim 10 , wherein the germanium is epitaxially grown over the second semiconductor material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2015
From: BALAKRISHNAN, KARTHIK; CHENG, KANGGUO; HASHEMI, POUYA; REZNICEK, ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 035961/0575 →