Controlled fin-merging for fin type FET devices
View Patent ↗A method for fabricating FET devices is disclosed. The method includes forming continuous fins of a semiconductor material and fabricating gate structures overlaying the continuous fins. After the fabrication of the gate structures, the method uses epitaxial deposition to merge the continuous fins to one another. Next, the continuous fins are cut into segments. The fabricated FET devices are characterized as being non-planar devices. A placement of non-planar FET devices is also disclosed, which includes non-planar devices that have electrodes, and the electrodes contain fins and an epitaxial layer which merges the fins together. The non-planar devices are so placed that their gate structures are in a parallel configuration separated from one another by a first distance, and the fins of differing non-planar devices line up in essentially straight lines. The electrodes of differing FET devices are separated from one another by a cut defined by opposing facets of the electrodes, with the opposing facets also defining the width of the cut. The width of the cut is smaller than one fifth of the first distance which separates the gate structures.
1. A method for fabricating FET devices, said method comprising:
forming continuous fins of a semiconductor material over a principal surface of a support member;
fabricating gate structures overlaying said continuous fins;
ensuing said fabricating of said gate structures, using an epitaxial deposition to merge said continuous fins to one another with an epitaxial layer;
ensuing said epitaxial deposition, cutting said continuous fins into segments, wherein each of said gate structures is comprised by one of said segments; and
characterizing said FET devices as being non-planar devices.
2. The method of claim 1 , wherein said method further comprises:
in forming said continuous fins, extending each one of said continuous fins in a length direction, and spacing said continuous fins apart of each other in a width direction, wherein said width direction is substantially perpendicular to said length direction;
in fabricating said gate structures, overlaying said continuous fins in said width direction, and spacing said gate structures apart of each other in said length direction; and
in cutting said continuous fins, performing said cutting along said width direction in-between pairs of said gate structures.
3. The method of claim 1 , wherein said continuous fins have top surfaces, which top surfaces are spaced away and are substantially in parallel with said principal surface of said support member, said method further comprises:
keeping said top surfaces clear from said epitaxial layer.
4. The method of claim 3 , wherein said method comprises:
covering said top surfaces with a hard-mask prior to said epitaxial deposition.
5. The method of claim 3 , wherein said method comprises:
etching away said epitaxial layer from said top surfaces after said epitaxial deposition.
6. The method of claim 2 , wherein said spacing separates said gate structures from one another by a first distance, and said cutting effects a cut separating said segments, wherein said cut has a width, said method comprises:
selecting said width to be smaller than one fifth of said first distance.
7. The method of claim 1 , wherein said method further comprises:
selecting said semiconductor material to be a silicon based single crystal material.
8. The method of claim 1 , wherein said method further comprises:
processing to conclusion said segments that comprise said gate structures, whereby completing fabrication of said non-planar devices.
9. The method of claim 1 , wherein said method further comprises:
selecting said non-planar devices to be FinFET devices.
10. The method of claim 1 , wherein said method further comprises:
selecting said non-planar devices to be TriGate devices.