Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET
View Patent ↗A method includes providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe. Each formed fin has a fin shape and fin location preserving hard mask layer on a top surface. The method also includes depositing Si on a first subset of the set of fins in what will be an nFET area; performing a Si—Ge inter-mixing process on the first subset of fins to reduce a concentration of Ge in the first subset while producing a Si—Ge intermix layer; removing the Si—Ge intermix layer leaving the first subset of fins having the reduced concentration of Ge, and forming a second subset of fins in what will be a pFET area. The second subset is also formed from the layer of SiGe and has a greater percentage of Ge than a percentage of Ge in the first subset of fins.
1. A structure comprising:
a substrate;
a first subset of fins defined in an nFET area of the structure, the first subset of fins being comprised of tensile strained substantially pure Si formed from an initial semiconductor layer disposed over the substrate, the initial semiconductor layer being comprised of a layer of Si 1-x Ge x having a first value of x; and
a second subset of fins defined in a pFET area of the structure, the second subset of fins being comprised of compressive strained Si 1-x Ge x formed from the initial semiconductor layer and having a second value of x that is greater than the first value of x; where
each fin of at least the first subset of fins is comprised of an overlying hard mask layer that preserves a location and shape of the first subset of fins during a process to reduce the value of x in the initial semiconductor layer.
2. The structure as in claim 1 , where the process comprises iterated steps of depositing Si on the first subset of the set of fins, performing a Si—Ge intermixing process and removing a resultant Si—Ge intermix layer.
3. The structure as in claim 1 , further comprising a dielectric layer disposed between each of the first and second subsets of fins and the substrate.
4. The structure as in claim 3 , where the substrate is comprised of Si.
5. The structure as in claim 3 , where the initial layer of semiconductor material is substantially lattice matched to the Si substrate.
6. A structure comprising:
a substrate;
a first subset of fins defined in an nFET area of the structure, the first subset of fins being comprised of tensile strained substantially pure Si formed from an initial semiconductor layer of Si—Ge disposed over the substrate; and
a second subset of fins defined in a pFET area of the structure, the second subset of fins being comprised of compressive strained Si—Ge formed from the initial semiconductor layer and having a greater percentage of Ge than a percentage of Ge in the first subset of fins; where
each fin of at least the first subset of fins is comprised of an overlying hard mask layer that preserves a location and shape of the first subset of fins during a process to reduce the amount of Ge in the initial semiconductor layer of Si—Ge.
7. The structure as in claim 6 , where the process comprises iterated steps of depositing Si on the first subset of the set of fins, performing a Si—Ge intermixing process and removing a resultant Si—Ge intermix layer.
8. The structure as in claim 6 , further comprising a dielectric layer disposed between each of the first and second subsets of fins and the substrate.
9. The structure as in claim 8 , where the substrate is comprised of Si.
10. The structure as in claim 8 , where the initial layer of semiconductor material is substantially lattice matched to the Si substrate.