Double aspect ratio trapping
A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure.
1. A semiconductor structure comprising:
a semiconductor substrate portion comprising a first semiconductor material having a first lattice constant;
a plurality of first semiconductor-containing pillar structures comprising a second semiconductor material having a second lattice constant that is greater than said first lattice extending upwards from a surface of said semiconductor substrate portion;
a plurality of second semiconductor-containing pillar structures comprising a third semiconductor material having a third lattice constant that is greater than said first lattice constant extending upwards from another surface of said semiconductor substrate portion;
a dielectric spacer laterally separating each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure, wherein each of said second semiconductor-containing pillar structures has a width that is different from a width of each of said first semiconductor-containing pillar structures;
wherein said second semiconductor material and said third semiconductor material each comprises a lower portion having a first defect density and an upper portion having a second defect density that is less than the first defect density;
further comprising a dielectric cap portion located on a topmost surface of each first semiconductor-containing pillar structure, wherein a topmost surface of said dielectric cap portion is coplanar with a topmost surface of each second semiconductor-containing pillar structure and a topmost surface of each dielectric spacer; and
wherein each of said second semiconductor-containing pillar structures has a height that is greater than a height of each of said first semiconductor-containing pillar structures.
2. The semiconductor structure of claim 1 , wherein said second semiconductor material and said third semiconductor material comprise a same semiconductor material.
3. The semiconductor structure of claim 1 , wherein said second semiconductor material comprises a different semiconductor material than said third semiconductor material.
4. The semiconductor structure of claim 1 , wherein said first semiconductor material is silicon and said second and third semiconductor materials are selected from germanium, an III-V compound semiconductor and an II-VI compound semiconductor.
5. The semiconductor structure of claim 1 , wherein a lower portion of each second semiconductor-containing pillar structure is embedded within an upper portion of said semiconductor substrate portion.
6. The semiconductor structure of claim 1 , wherein said second and third semiconductor material have an epitaxial relationship with said semiconductor substrate portion.
7. The semiconductor structure of claim 1 , wherein a topmost surface of each second semiconductor-containing pillar structure is higher than a topmost surface of each first semiconductor-containing pillar structure.
8. The semiconductor structure of claim 7 , wherein a bottommost surface of each second semiconductor-containing pillar structure is lower than a bottommost surface of each first semiconductor-containing pillar structure.
9. The semiconductor structure of claim 1 , wherein said surface of said semiconductor substrate portion that contains each first semiconductor-containing pillar structure is raised relative to said another surface of said semiconductor portion that contains each second semiconductor-containing pillar structure.
10. The semiconductor structure of claim 1 , wherein one of said second semiconductor-containing pillar structures is present between a nearest neighboring pair of first semiconductor-containing pillar structures.
11. A semiconductor structure comprising:
a semiconductor substrate portion comprising a first semiconductor material having a first lattice constant;
a plurality of alternating first semiconductor-containing pillar structures and second semiconductor-containing pillar structures, wherein each first semiconductor-containing pillar structure comprises a second semiconductor material having a second lattice constant that is greater than said first lattice extending upwards from a surface of said semiconductor substrate portion,
wherein each second semiconductor-containing pillar structure comprises a third semiconductor material having a third lattice constant that is greater than said first lattice constant extending upwards from another surface of said semiconductor substrate portion; and
a dielectric spacer laterally separating each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure, wherein each of said second semiconductor-containing pillar structures has a width that is different from a width of each of said first semiconductor-containing pillar structures;
wherein said second semiconductor material and said third semiconductor material each comprises a lower portion having a first defect density and an upper portion having a second defect density that is less than the first defect density;
further comprising a dielectric cap portion located on a topmost surface of each first semiconductor-containing pillar structure, wherein a topmost surface of said dielectric cap portion is coplanar with a topmost surface of each second semiconductor-containing pillar structure and a topmost surface of each dielectric spacer; and
wherein each of said second semiconductor-containing pillar structures has a height that is greater than a height of each of said first semiconductor-containing pillar structures.
12. The semiconductor structure of claim 11 , wherein a topmost surface of each second semiconductor-containing pillar structure is higher than a topmost surface of each first semiconductor-containing pillar structure.
13. The semiconductor structure of claim 12 , wherein a bottommost surface of each second semiconductor-containing pillar structure is lower than a bottommost surface of each first semiconductor-containing pillar structure.
14. The semiconductor structure of claim 11 , wherein said surface of said semiconductor substrate portion that contains each first semiconductor-containing pillar structure is raised relative to said another surface of said semiconductor portion that contains each second semiconductor-containing pillar structure.