Germanium dual-fin field effect transistor

1. A method, comprising:

forming a fin on a substrate;

forming a gate stack over a portion of the fin;

growing source and drain regions over the fin, on both sides of the gate stack;

removing the gate stack;

epitaxially growing a pair of conducting channels on opposite sides of the fin, between the source and drain regions; and

removing the fin from between the pair of conducting channels.

2. The method of claim 1 , wherein the forming the fin comprises:

growing an epitaxial layer of a semiconductor material on the substrate;

patterning the epitaxial layer of semiconductor material using a hard mask, to form the fin.

3. The method of claim 1 , wherein the fin is formed from N + doped silicon.

4. The method of claim 3 , wherein the growing the source and drain regions comprises:

depositing N ++ doped silicon over the fin.

5. The method of claim 4 , wherein a doping concentration of the N+ doped silicon is between approximately 5e18 and 5e19 electrons per cubic centimeter, and a doping concentration of N++ doped silicon is above approximately 1e20 electrons per cubic centimeter.

6. The method of claim 1 , further comprising:

depositing a hard mask over the fin, prior to forming the gate stack;

recessing the fin under edges of the hard mask, prior to epitaxially growing the pair of conducting channels, such that the fin and the hard mask collectively form a T-shaped profile; and

removing the hard mask from the fin, subsequent to epitaxially growing the pair of conducting channels.

7. The method of claim 6 , further comprising:

depositing an organic planarizing layer or a flowable oxide above the fin, subsequent to removing the hard mask; and

removing the organic planarizing layer or flowable oxide, subsequent to removing the fin.

8. The method of claim 1 , further comprising:

depositing an inter-layer dielectric material over the source and drain regions; and

forming at least one contact in the inter-layer dielectric material, down to the source and drain regions.

9. The method of claim 1 , further comprising:

depositing a high-k dielectric material over the pair of conducting fins; and

depositing a gate over the high-k dielectric material.

10. The method of claim 1 , wherein the pair of conducting channels is formed of germanium.

11. The method of claim 1 , wherein the pair of conducting channels and the source and drain regions comprise portions of a field effect transistor.

12. The method of claim 1 , wherein the source and drain regions are formed from a first material, and the pair of conducting channels is formed from a second material that is different from the first material.

13. A method, comprising:

fabricating a dummy structure

growing source and drain regions on opposite sides of the dummy structure;

removing a portion of the dummy structure after growing the source and drain regions;

epitaxially growing a pair of conducting channels in place of the portion of the dummy structure that was removed; and

removing a remainder of the dummy structure from between the pair of conducting channels.

14. The method of claim 13 , wherein the source and drain regions are formed from a first material, and the pair of conducting channels is formed from a second material that is different from the first material.

15. The method of claim 14 , wherein the first material is doped silicon.

16. The method of claim 14 , wherein the second material is germanium.

17. The method of claim 13 , wherein the pair of conducting channels and the source and drain regions comprise portions of a field effect transistor.

18. The method of claim 13 , further comprising:

depositing an inter-layer dielectric material over the source and drain regions; and

forming at least one contact in the inter-layer dielectric material, down to the source and drain regions.

19. The method of claim 13 , further comprising:

depositing a high-k dielectric material over the pair of conducting fins; and

depositing a gate over the high-k dielectric material.