Field effect transistor contacts
View Patent ↗A method comprises forming a first gate of a first field effect transistor (FET) device over a first channel region of a first fin arranged on a substrate, forming a second gate of a second FET device over a second channel region of a second fin arranged on the substrate, the second channel region having a width that is greater than a width of the first channel region, etching to remove portions of the insulator material and define a first cavity that exposes an active region of the first FET device and a second cavity that exposes an active region of the second FET device, and depositing a conductive material in the first cavity to define a first contact and depositing a conductive material in the second cavity to define a second contact, the second contact having a width that is greater than a width of the first contact.
1. A method for forming a field effect transistor device, the method comprising:
forming a first gate stack of a first field effect transistor (FET) device over a first channel region of a fin arranged on a substrate;
forming a second gate stack of a second FET device over a second channel region of the fin arranged on the substrate, the second channel region having a width that is greater than a width of the first channel region;
patterning a masking layer over portions of an insulator material, the insulator material arranged over portions of the fin and the substrate;
etching to remove exposed portions of the insulator material and define a first cavity that exposes an active region of the first FET device and a second cavity that exposes an active region of the second FET device; and
depositing a conductive material in the first cavity to define a first contact and depositing a conductive material in the second cavity to define a second contact, the second contact having a width that is greater than a width of the first contact.
2. The method of claim 1 , further comprising planarizing the deposited conductive material to further define the first contact and the second contact.
3. The method of claim 1 , further comprising removing the masking layer prior to depositing the conductive material.
4. The method of claim 1 , wherein the fin includes a semiconductor material.
5. The method of claim 1 , wherein the insulator material includes an oxide material.
6. The method of claim 1 , wherein the insulator material includes a liner layer disposed on the fin.
7. A method for forming a field effect transistor (FET) device, the method comprising:
forming a first gate stack of a first FET device over a first channel region of a fin arranged on a substrate;
forming a second gate stack of a second FET device over a second channel region of the fin arranged on the substrate, the second channel region having a width that is greater than a width of the first channel region;
forming an insulator material layer over exposed portions of the fin and the substrate;
patterning a masking layer over portions of the insulator material layer;
etching to remove exposed portions of the insulator material layer to define a first cavity that exposes an active region of the first FET device and a second cavity that exposes an active region of the second FET device; and
depositing a conductive material in the first cavity to define a first contact and depositing a conductive material in the second cavity to define a second contact, the second contact having a width that is greater than a width of the first contact.
8. The method of claim 7 , further comprising planarizing the deposited conductive material to further define the first contact and the second contact.
9. The method of claim 7 , further comprising removing the masking layer prior to depositing the conductive material.
10. The method of claim 7 , wherein the fin includes a semiconductor material.
11. The method of claim 7 , wherein the insulator material includes an oxide material.
12. The method of claim 7 , wherein the insulator material includes a liner layer disposed on the fin.