Semiconductor device including gate channel having adjusted threshold voltage
View Patent ↗A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.
1. A semiconductor device comprising:
a semiconductor substrate including an nFET portion and a pFET portion separately located from the nFET portion;
at least one first semiconductor fin formed on the nFET portion, the at least one first semiconductor fin having an nFET channel region interposed between a pair of nFET source/drain regions; and
at least one second semiconductor fin formed on the pFET portion, the at least one second semiconductor fin having a pFET channel region interposed between a pair of pFET source/drain regions, the pFET channel region including an etched portion of the at least one second semiconductor fin, and wherein the etched portion has a first thickness that is less than a second thickness of the at least one first semiconductor fin; and
an epitaxial liner formed only on the pFET channel region such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel region
wherein the epitaxial liner is formed on the etched portion, the combination of the etched portion and the epitaxial liner defining a third thickness that is equal to the second thickness of the at least one first semiconductor fin.
2. The semiconductor device of claim 1 , wherein the nFET source/drain regions and the pFET source/drain regions each exclude the epitaxial liner.
3. The semiconductor device of claim 2 , wherein the epitaxial liner comprises silicon germanium (SiGe) formed in a middle portion of the at least one second semiconductor fin formed on the pFET portion, and the middle region of that at least one second semiconductor fin formed on the nFET portion is formed from only Si.
4. The semiconductor device of claim 3 , wherein the at least one second semiconductor fin formed on the pFET portion includes a middle portion defined by the SiGe channel region and side portions consisting of Si formed at opposing sides of the middle portion, and wherein the at least one first semiconductor fin formed on the nFET portion includes a Si middle portion consisting of only Si and side portions consisting of Si formed at opposing sides of the Si middle portion.
5. The semiconductor device of claim 4 , wherein the second threshold voltage is less than the first threshold voltage.
6. The method of claim 1 , wherein the semiconductor substrate has multiple pFET regions, each pFET channel region having a different concentration of SiGe with respect to one another to form different respective threshold voltages.
7. The semiconductor device of claim 6 , wherein the multiple pFET regions includes the first pFET region having a SiGe concentration of 25%, the second pFET region having a SiGe concentration of 50%, and a third pFET region having a SiGe concentration of 75%, wherein a third threshold voltage of the third pFET region is less than the first and second threshold voltages.