Germanium dual-fin field effect transistor
In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.
1. A method for fabricating a pair of fins for a field effect transistor, the method comprising:
forming a silicon fin on a substrate;
forming a gate stack over a portion of the silicon fin;
growing source and drain regions over the silicon fin, on both sides of the gate stack;
removing the gate stack;
epitaxially growing germanium on both sides of the silicon fin in the region where the gate stack was positioned, to form two germanium channels; and
removing the silicon fin from between the two germanium channels, such that the two germanium channels form the pair of fins.
2. The method of claim 1 , wherein the forming the silicon fin comprises:
growing an epitaxial layer of silicon on the substrate;
patterning the epitaxial layer of silicon using a hard mask, to form the fin.
3. The method of claim 1 , wherein the silicon fin is formed from N + doped silicon.
4. The method of claim 3 , wherein the growing the source and drain regions comprises:
depositing N ++ doped silicon over the silicon fin.
5. The method of claim 4 , wherein a doping concentration of the N+ doped silicon is between approximately 5e18 and 5e19 electrons per cubic centimeter, and a doping concentration of N++ doped silicon is above approximately 1e20 electrons per cubic centimeter.
6. The method of claim 1 , further comprising:
depositing a hard mask over the silicon fin, prior to forming the gate stack;
recessing the silicon fin under edges of the hard mask, prior to epitaxially growing the germanium, such that the fin and the hard mask collectively form a T-shaped profile; and
removing the hard mask from the silicon fin, subsequent to epitaxially growing the germanium.
7. The method of claim 6 , further comprising:
depositing an organic planarizing layer or a flowable oxide above the silicon fin, subsequent to removing the hard mask; and
removing the organic planarizing layer or flowable oxide, subsequent to removing the silicon fin.
8. The method of claim 1 , further comprising:
depositing an inter-layer dielectric material over the source and drain regions; and
forming at least one contact in the inter-layer dielectric material, down to the source and drain regions.
9. The method of claim 1 , further comprising:
depositing a high-k dielectric material over the pair of fins; and
depositing a gate over the high-k dielectric material.